KR950025785A - Semiconductor Memory Device with Address Transition Detection Circuit - Google Patents

Semiconductor Memory Device with Address Transition Detection Circuit Download PDF

Info

Publication number
KR950025785A
KR950025785A KR1019940003254A KR19940003254A KR950025785A KR 950025785 A KR950025785 A KR 950025785A KR 1019940003254 A KR1019940003254 A KR 1019940003254A KR 19940003254 A KR19940003254 A KR 19940003254A KR 950025785 A KR950025785 A KR 950025785A
Authority
KR
South Korea
Prior art keywords
semiconductor memory
memory device
memory cell
control signal
pulse
Prior art date
Application number
KR1019940003254A
Other languages
Korean (ko)
Other versions
KR970004816B1 (en
Inventor
황상기
조성희
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019940003254A priority Critical patent/KR970004816B1/en
Publication of KR950025785A publication Critical patent/KR950025785A/en
Application granted granted Critical
Publication of KR970004816B1 publication Critical patent/KR970004816B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

본 발명은 메모리 셀 어레이와, 외부에서 입력되는 어드레스 신호를 디코딩하여 상기 메모리 셀 어레이 내의 메모리 셀을 지정하기 위한 디코더를 구비하는 반도체 메모리 장치에 있어서, 상기 어드레스 신호의 천이를 감지하기 위한 어드레스 천이 검출 수단과, 상기 어드레스 천이 검출수단에 접속하며 외부 입력단자에 입력된 노이즈에 의해 발생된 비정상적인 펄스를 소정의 펄스 폭을 가지도록 증폭하는 펄스 증폭수단과, 상기 펄스 증폭수단에 접속하며 상기 펄스 증폭회로의 출력 신호를 입력하여 일정한 펄스 폭을 가지는 프리아차지 및 아퀼라이즈 제어 신호를 발생하는 제어신호 발생수단을 구비함을 특징으로 하는 반도체 메모리 장치를 구비함을 특징으로 한다.A semiconductor memory device comprising a memory cell array and a decoder for decoding an address signal input from an external device and designating a memory cell in the memory cell array, wherein the address transition detection for detecting a transition of the address signal is performed. Means for amplifying an abnormal pulse generated by noise input to an external input terminal, said pulse amplifying means connected to said address transition detecting means, and said pulse amplifying means connected to said pulse amplifying means. And a control signal generating means for generating a precharge and aquilaise control signal having a predetermined pulse width by inputting an output signal of the semiconductor memory device.

본 발명에 의한 반도체 메모리 장치에 의하여 외부 입력 단자에 입력된 노이즈에 무관하게 일정한 펄스 폭을 가지는 프리차아지 및 아퀼라이즈 제어 신호를 발생하여 데이타 라인의 프리차아지 및 아퀼라이즈 동작이 충분하게 이루어져 정상적인 동작을 수행될 수 있는 효과가 있다.The semiconductor memory device according to the present invention generates a precharge and aquilaise control signal having a constant pulse width irrespective of noise input to an external input terminal, thereby sufficiently precharging and aquilizing the data line. There is an effect that the operation can be performed.

Description

어드레스 천이 검출 회로를 내장하는 반도체 메모리 장치Semiconductor Memory Device with Address Transition Detection Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제8도는 본 발명에 따른 반도체 메모리 장치의 개략적 블럭 다이어그램.8 is a schematic block diagram of a semiconductor memory device according to the present invention.

Claims (4)

메모리 셀 어레이와, 외부에서 입력되는 어드레스 신호를 디코딩하여 상기 메모리 셀 어레이 내의 메모리셀을 지정하기 위한 디코더를 구비하는 반도체 메모리 장치에 있어서, 상기 어드레스 신호의 천이를 감지하기 위한 어드레스 천이 검출 수단과, 상기 어드레스 천이 검출 수단에 접속하며 외부 입력 단자에 입력된 노이즈에 의해 발생된 비정상적인 펄스를 소정의 펄스 폭을 가지도록 증폭하는 펄스증폭 수단과, 상기 펄스 증폭수단에 접속하며 상기 펄스 증폭회로의 출력 신호를 입력하여 일정한 펄스 폭을 가지는 프리차아지 및 이퀄라이즈 제어 신호를 발생하는 제어신호 발생 수단을 구비함을 특징으로 하는 반도체 메모리 장치.A semiconductor memory device having a memory cell array and a decoder for decoding an address signal input from an external device and designating a memory cell in the memory cell array, comprising: address transition detection means for detecting a transition of the address signal; Pulse amplifying means connected to the address transition detecting means and amplifying an abnormal pulse generated by noise input to an external input terminal to have a predetermined pulse width, and connected to the pulse amplifying means and output signal of the pulse amplifying circuit. And control signal generation means for generating a precharge and an equalization control signal having a predetermined pulse width by inputting the input signal. 제1항에 있어서, 상기 제어신호 발생수단은 칩 내부의 워드라인 지여니을 트래킹 할 수 있음을 특징으로 하는 반도체 메모리 장치.2. The semiconductor memory device according to claim 1, wherein said control signal generating means can track word line genie within a chip. 제1항에 있어서, 상기 프리차아지 및 이퀄라이즈 제어 신호의 펄스 폭은 적어도 10ns이상임을 특징으로 하는 반도체 메모리 장치.The semiconductor memory device of claim 1, wherein a pulse width of the precharge and equalization control signals is at least 10 ns or more. 제1항에 있어서, 상기 제어신호 발생 수단은 메모리 셀 어레이로부터 출력되는 셀 데이타를 증폭하여 상기 프리차아지 및 이퀄라이즈 제어신호에 의해 제어되는 센스엠프와, 상기 센스엠프에 접속하며 출력데이타를 버퍼링하는 데이타 출력버퍼를 제어함을 특징으로 하는 반도체 메모리 장치.2. The apparatus of claim 1, wherein the control signal generating means amplifies the cell data output from the memory cell array to connect to the sense amplifier controlled by the precharge and equalization control signals, and to connect the sense amplifier to buffer the output data. And a data output buffer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940003254A 1994-02-23 1994-02-23 A semiconductor memory device containing an address transition detection circuit KR970004816B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940003254A KR970004816B1 (en) 1994-02-23 1994-02-23 A semiconductor memory device containing an address transition detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940003254A KR970004816B1 (en) 1994-02-23 1994-02-23 A semiconductor memory device containing an address transition detection circuit

Publications (2)

Publication Number Publication Date
KR950025785A true KR950025785A (en) 1995-09-18
KR970004816B1 KR970004816B1 (en) 1997-04-04

Family

ID=19377639

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940003254A KR970004816B1 (en) 1994-02-23 1994-02-23 A semiconductor memory device containing an address transition detection circuit

Country Status (1)

Country Link
KR (1) KR970004816B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100268929B1 (en) * 1997-12-22 2000-12-01 김영환 Address transition detection circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100268929B1 (en) * 1997-12-22 2000-12-01 김영환 Address transition detection circuit

Also Published As

Publication number Publication date
KR970004816B1 (en) 1997-04-04

Similar Documents

Publication Publication Date Title
KR920010639A (en) Detection amplifier for ferroelectric memory and its detection method
KR930003153A (en) Semiconductor integrated circuit device
KR960042374A (en) Semiconductor memory device with control circuit and control method
KR900010788A (en) Output feedback control circuit of integrated circuit device
KR970076810A (en) Semiconductor memory
KR880008334A (en) How to detect data at high speed and its dynamic semiconductor memory
KR960008849A (en) Semiconductor memory
KR920003169A (en) SAM data access circuit with low operating current and method
KR890013658A (en) Semiconductor memory device
KR930018583A (en) Semiconductor memory including address change detection circuit
KR920022306A (en) Input / output line precharge method of memory device
KR970012694A (en) Fast read semiconductor memory
KR950025785A (en) Semiconductor Memory Device with Address Transition Detection Circuit
KR970003259A (en) Page Mode Mask ROM Using 2 Stage Latch Circuit and Its Control Method
KR100431477B1 (en) Semiconductor memory device
KR0136668B1 (en) Pulse generating circuit of memory
KR980004981A (en) Data I / O Line Loading Reduction Device in Multi-Bank Structure
KR100200919B1 (en) Write road control circuit of semiconductor memory device using address transition sensor
KR930010990A (en) Circuit for Improving Speed in Semiconductor Memory Device
KR970051158A (en) Memory devices
KR930022381A (en) Column I / O Structure of Semiconductor Memory Device
KR970012703A (en) Semiconductor Memory Device Eliminating Address Disturbance
KR970003272A (en) High speed test circuit
KR930006546A (en) Precharge and Equalization Circuit of Data Input / Output Lines
JPH087575A (en) Sense amplifier and semiconductor memory

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
J2X1 Appeal (before the patent court)

Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL

G160 Decision to publish patent application
B701 Decision to grant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20020605

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee