KR970004816B1 - A semiconductor memory device containing an address transition detection circuit - Google Patents

Abstract

A semiconductor memory device includes an address transition detector having a stable operation characteristic about a noise applied to an external input terminal. A semiconductor memory device includes: address transition detector for sensing a transition of the address signal; a pulse amplifier which is connected to the address transition detector, and amplifies abnormal pulse generated by the noises from the external input terminal; and a control signal generator which is connected to the pulse amplifier, inputs an output signal of the pulse amplifier, and generates a precharge/equalize control signal having a constant pulse width.

Description

Semiconductor Memory Device with Address Transition Detection Circuit

1 is a schematic block diagram of a semiconductor memory device according to the prior art.

2 is a diagram showing a schematic configuration of an address transition detection circuit according to FIG.

3 is a detailed circuit diagram of a short pulse generating circuit according to FIG.

4 shows a detailed circuit of the summator according to FIG. 2;

5 shows a detailed circuit of the word line tracking pulse generation circuit according to FIG.

6 is a timing diagram at the time of normal address input according to FIGS.

FIG. 7 is a timing diagram at the time of noise input address input according to FIGS.

8 is a schematic block diagram of a semiconductor memory device according to the present invention.

9 shows a first embodiment of the pulse amplifier circuit according to FIG.

10 shows a second embodiment of the pulse amplifier circuit according to FIG.

11 is a timing diagram at the time of normal address input according to FIGS.

12 is a timing diagram at the time of noise input address input according to FIGS. 8 to 11;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an address transition detector (ATD) which can have a stable operation characteristic against noise introduced into an external input terminal.

In general, most of the asynchronous semiconductor memory devices currently in use include an ATD circuit that detects a change in an address signal and generates a pulse as a technique for generating a clock therein. By using such an ATD circuit, each circuit inside the chip is driven using pulses generated from the ATD circuit, thereby reducing power consumption and speeding up signal transmission.

The ATD circuit detects this when an address signal input from the outside transitions and generates a pulse, and the semiconductor memory device operates according to the pulse.

The configuration of FIG. 1 is a conventional configuration in the art, and is connected to a memory cell array 20 having a plurality of memory cells and an input buffer 4 buffering an address signal Addx input from the outside, and outputted from the input buffer 4. X, Y predecoder section 14, X-decoder 16, and Y-decoder 18 for decoding the memory cells in the memory cell array 20 by decoding them, and ATD circuit 6 for detecting a transition of an externally input address signal; Connects to the ATD circuit 6 and inputs the output signal SMO output from the ATD circuit 6 to generate the precharge and equalization control signal EPS that controls the precharge and equalization operation of the sense amplifier 24, thereby delaying the word line inside the chip. Wordline tracking pulse generation circuit 8 for tracking and tracking, and output from memory cell array 20 through Y-pass 22 It amplifies the data, and connected to a sense amplifier 24 which is controlled by the pre-equalizing the charge and EPS control signal outputted from the tracking word line pulse generating circuit 8 and sense amplifier 24 and the output enable signal It is composed of a data output buffer 26 that is controlled by an input buffer 12 that buffers the output data, and an output pad 28 that connects to the data output buffer 26.

A characteristic of the operation of the semiconductor memory device shown in FIG. 1 is that the ATD detection circuit 6 detects a change in any one of the addresses Addx input from the outside and generates a pulse. The pulse generated from the ATD circuit 6 is input to the wordline tracking pulse generator circuit 8, and the wordline tracking pulse generator circuit 8 generates a precharge and equalization control signal EPS which controls the sense amplifier 24. Accordingly, the sense amplifier 24 controls the operation of transmitting data read from 20 to the memory cell array to the outside.

2 is a diagram showing the schematic configuration of the address transition detection circuit 6 according to FIG. The circuit shown in Fig. 2 is connected to the input terminals 30 ... 34 of the external addresses Ax0 ... Axn to format the external addresses Ax0 ... Axn to the internal addresses Ap0 ... Apn. Output signals of the address detection short pulse generator circuit 36 ... 40 connected to .56, 58 and the address detection short pulse generator circuit (SPG) 36 ... 40. The ATD circuit 6 constitutes a summator 42 that outputs a control signal SMO for controlling the word line tracking pulse generation circuit 8 by inputting the respective signals.

3 is a detailed circuit diagram of the short pulse generator according to FIG. The short pulse generator of FIG. 3 enters the internal addresses Ap0 ... Apn of FIG. 2 and passes through the delay circuit 66. When any one of the internal addresses Ap0 ... Apn transitions, the inverter 62 is connected to the NAND gate 60. Or short pulse Sp0, respectively via NOR gate 64 ... Spn, This will occur. At this time, the delay circuit 66 has an odd delay stage.

4 is a detailed circuit diagram of the summator 42 according to FIG. The fourth summator is output signal Sp0, of short pulse generating circuit 36 ... 40 for address detection. ... Spn, Are respectively inputted to output a control signal SMO for controlling the word line tracking pulse generation circuit 8 of FIG. As shown, Sp0, which is an output signal of the short pulse generating circuit 36 ... 40 for address detection, ... Spn, Is input to the gate terminals of NMOS transistors 80,82,84,86 connected in parallel between node A and ground voltage. The summator circuit of FIG. 4 has a PMOS transistor 68 in which a source terminal is connected to the power supply voltage VCC, a drain terminal is connected to the node A, a gate terminal is controlled by the output signal of the inverter 78, and a source terminal is connected to the power supply voltage VCC. An output signal SMO having a PMOS transistor 70 whose drain terminal is connected to the node A and whose gate terminal is controlled by the output signal of the inverter 72, and which controls the word line tracking pulse generation circuit through the inverter 74 connected to the node A. Occurs. The delay circuit 76 inputs the output signal of the inverter 72 to delay a predetermined time, and the signal output from the delay circuit 76 controls the gate terminal of the PMOS transistor 68 through the inverter 78.

In the summator circuit of FIG. 4, the pulse Sp0 generated from the short pulse generating circuits 36 ... 40 of FIG. ... Spn, When either of them is input as a logic high state pulse, it causes any one of the NMOS transistors 80 ... 86 to conduct, from which a pulse SMO in a logic low state is generated.

5 is a diagram illustrating a detailed circuit of the word line tracking pulse generation circuit according to FIG. 1. The word line tracking pulse generation circuit shown in FIG. 5 inputs the control signal SMO generated from the ATD circuit to generate the precharge and equalization control signal EPS of the sense amplifier. The word line tracking pulse generation circuit shown in FIG. 5 includes an inverter 88 for inputting and inverting a control signal SMO generated from an ATD circuit, a resistor R1 connected between the inverter 88 and a node C, and a node C and a ground voltage VSS. A capacitor C1 connected to the resistor C, a resistor RWL connected between the node C and the node D, a PMOS transistor 90 having a source terminal connected to the power supply voltage VCC, a drain terminal connected to the node D, and a control signal SMO applied to the gate terminal; Capacitor C2 connected between node D and ground voltage, resistor R2 connected to node D, inverter 92 connected to resistor R2, and output signal of NAND gate 94 for inputting the output signal and control signal SMO of inverter 92; And inverter 96 for outputting precharge and equalization control signals EPS by inverting.

When the data read from the memory cell array is sensed by the sense amplifier after precharging and equalizing the data line at the load of the sense amplifier, the signal of the word line is within the pulse width of the precharge and equalization control signal. It must be operated with a margin in order to correctly read the memory cells of the selected word line. In the word line tracking circuit of FIG. 5, the resistor RWL has a change in the delay of the word line and a change in the pulse width of the control signal EPS for precharging and equalizing the sense amplifier according to the change of the characteristics of the polysilicon forming the word line. Will change correspondingly. In a semiconductor memory device having an operating speed of about 50 ns or less, the word line delay is only a few ns, so that even if a process change occurs, the word line delay is not large. However, in a semiconductor memory device having an operating speed of about 100 ns, if a process change occurs, the word line delay is about tens of ns, which significantly affects the operation of the semiconductor memory. Therefore, the process characteristics of polysilicon, which is the material constituting the word line, are changed by constructing the resistor RWL constituting the word line tracking pulse generating circuit of gel 5 degrees using the same material as the polysilicon constituting the word line. Even if the delay is changed, the delay of the word line and the pulse delay of the precharge and equalization control signals coincide, so that normal data is sensed by the sense amplifier after the word line change, thereby preventing malfunction.

The operation of the semiconductor memory device according to the related art shown in FIG. 1 will be described in more detail with reference to the timing diagrams shown in FIGS. 6 and 7. FIG. 6 is a timing diagram at the time of a normal address input, and FIG. 7 is a timing diagram at the input of a noise introduced address. As shown in FIG. 6, since the normal address is input from the outside, the ATD circuit shown in FIG. 2 generates the internal address Apn, and corresponds to the short pulse Spn, Is generated. However, when the address into which the noise input to the external input terminal is input as shown in FIG. 7 is input, the signal when the pulse width of the output signal SMO generated from the ATD circuit is the normal operation shown in FIG. It will be much shorter than the pulse width of the SMO. The pulse width of the output signal EPS of the word line tracking pulse generation circuit 8 is also very short due to the output signal SMO of the summator having such a short pulse width. In other words, the precharge and equalize operation of the data line in the load of the sense amplifier is possible only when a certain amount of time, that is, about 10-20 ns is required, but the output signal SMO of the ATD circuit having the short pulse of 10 ns or less Since the precharge and equalization operations of the data lines are not sufficiently performed, the wrong data is sensed by the sense amplifier and latched in the data output buffer 26 to cause a malfunction.

Accordingly, an object of the present invention is to generate a precharge and equalization control signal having a constant pulse width irrespective of noise input to an external input terminal, so that the precharge and equalize operations of the data line are sufficient to perform normal operation. A semiconductor memory device is provided.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device having a memory cell array and a decoder for decoding an externally input address signal to designate a memory cell in the memory cell array. An address transition detecting means, a pulse amplifying means connected to the address transition detecting means and amplifying an abnormal pulse generated by noise input to an external input terminal to have a predetermined pulse width, and connected to the pulse amplifying means, And a control signal generating means for inputting an output signal of a pulse amplifying circuit to generate a precharge and an equalizing control signal having a constant pulse width.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

In the case where the components of a conventional semiconductor memory device are the same as in the present invention, the same reference numerals are used.

8 is a schematic block diagram of a semiconductor memory device according to the present invention. The semiconductor memory device shown in FIG. 8 is connected to a memory cell array 20 having a plurality of memory cells and an input buffer 4 buffering an address signal Addx input from the outside, and decodes the address signal Add output from the input buffer 4. X, Y predecoder 14, X-decoder 16, and Y-decoder 18 for designating memory cells in the memory cell array 20, ATD circuit 6 for detecting a transition of an externally input address signal, and ATD circuit 6 A pulse amplifying circuit 98 connected to the pulse amplifying circuit 98 and a pulse amplifying circuit 98 for amplifying abnormal pulses generated by noise input to an external input terminal by inputting an output signal SMO output from the ATD circuit 6; Precharge and equalizer control the precharge and equalization behavior of the sense amplifier 24 by inputting the output signal ASMO Word line tracking pulse generation circuit 8, which generates the control signal EPS to track the word line delay in the chip, and amplifies the cell data output from the memory cell array 20 through Y-pass 22, thereby word line dragging. The output enable signal connected to the sense amplifier 24 controlled by the precharge and the equalizing control signal EPS output from the pulse generator circuit 8 and the sense amplifier 24. It is composed of a data output buffer 26 that is controlled by an input buffer 12 that buffers the output data, and an output pad 28 that connects to the data output buffer 26.

FIG. 1 uses a wordline tracking pulse generation circuit to match the signal delay caused by process variation between the precharge and equalization control signal EPS pulses generated corresponding to the word line delay and the signal SMO generated from the ATD circuit. In the semiconductor memory device, the pulse amplifier circuit 98 is provided to prevent malfunctions occurring when unwanted noise is input to the external input terminal.

9 and 10 show an embodiment of the pulse amplifier circuit 98 of the semiconductor memory device according to the present invention.

A first embodiment of the pulse amplification circuit of FIG. 9 includes an NAND gate 106 that gates an output signal SMO generated from an ATD circuit through an inverter 102 and an inverter 104, and an inverter connected to an output signal of the NAND gate 106. 108, a NAND gate 114 for gating the output signal of the inverter 108 and the output signal of the inverter 108 through the inverters 110 and 112, and a final output signal ASMO for inverting the output signal of the NAND gate 114; An inverter 116 is provided.

The second embodiment of the pulse amplifying circuit of FIG. 10 inputs the output signal SMO and the output signal SMO generated from the ATD circuit to the inverter 117, connects the output signal of the 117 to the inverter 118 and the NOR gate 122, and passes the inverters 118 and 120. A NOR gate 122 gating the generated signal and an output signal from the NOR gate 122 to the inverter 123 and a NOR gate connected to the inverter 123 and the NOR gate 128 and gated through the inverter 126 to the output signal of the NOR gate 122 And the inverters 130 and 132 for inputting the output signal of the gate 128 and the NOR gate 128 to generate the final output signal ASMO.

The pulse amplifier circuits shown in FIGS. 9 and 10 input the output signal SMO of the ATD circuit 6 to amplify and stabilize the noise signal input to the external input terminal.

By inputting the output signal SMO of the ATD circuit 6, the pulse amplification circuit shown in FIG. 9 or FIG. 10 generates the output signal ASMO. In the semiconductor memory device according to the present invention of FIG. 8, the output signal ASMO generated from the pulse amplifier circuit 98 is input to the word line tracking pulse generator circuit 8 to control precharge and equalization of the data lines in the load of the sense amplifier 24. Generates signal EPS. The configuration of the word line tracking pulse generation circuit shown in FIG. 8 has the same structure as the word line tracking pulse generation circuit used in the semiconductor memory device according to the conventional technique shown in FIG.

Only the output signal SMO generated from the ATD circuit is conventionally input, but in the present invention, the output signal ASMO generated from the pulse amplifier circuit 98 is input.

The pulse width of the precharge and equalization control signal EPS of the sense amplifier 24 generated from the wordline tracking pulse generator circuit 8 has a pulse width of approximately tens of ns, which is the time required for precharging and equalizing the data line. to be. If the pulse width of the precharge and equalization control signal EPS decreases more than normal due to some condition, the data line may sense memory cell data without being sufficiently precharged and equalized, thereby causing a malfunction.

The operation of the semiconductor memory device according to the technique of the present invention shown in FIG. 8 will be described in more detail with reference to the timing diagrams shown in FIGS. 11 and 12. FIG.

FIG. 11 is a timing diagram at the time of a normal address input, and FIG. 12 is a timing diagram at the input of a noise input address. As shown in FIG. 11, since the normal address is input from the outside, the ATD circuit 6 shown in FIG. 8 generates the internal address Apn as in the prior art, respectively, and corresponds to the internal address, sort pulse Spn, Is generated. The output signal generated from the ATD circuit 6 generates the signal ASMO through the pulse amplifier circuit 98, and the word line tracking pulse generator circuit 8 inputs the signal ASMO to transfer the precharge and equalization control signals EPS to the sense amplifier 24. Output

In addition, as shown in FIG. 12, when the noise input address is input to the external input terminal, the signal ASMO having a stable pulse width is input through the pulse amplifier circuit 98 by inputting the output signal SMO of the ATD circuit 6. Is generated. Accordingly, since the time for sufficient precharge and equalization operation of the data line is secured in the load of the sense amplifier, stable operation can be performed.

It will be readily understood by those skilled in the art that the semiconductor memory device according to the present invention as described above can be variously implemented within the scope of the spirit of the present invention. For example, it is apparent that the pulse amplifier circuits shown in FIGS. 9 and 10 can be easily implemented as circuit configurations different from those of the circuits shown in FIGS. 9 and 10.

As described above, the semiconductor memory device according to the present invention generates a precharge and equalization control signal having a constant pulse width irrespective of noise input to an external input terminal, thereby precharging and equalizing the data line. There is an effect that can be made sufficiently to perform a normal operation.

Claims (4)

A semiconductor memory device comprising a memory cell array and a decoder for decoding an externally input address signal to designate a memory cell in the memory cell array, comprising: address transition detecting means for detecting a transition of the address signal; A pulse amplifying means connected to the address transition detecting means and amplifying an abnormal pulse generated by noise input to an external input terminal to have a predetermined pulse width, and an output signal of a sound pulse amplifying circuit connected to the pulse amplifying means. And control signal generation means for generating a precharge and an equalization control signal having a predetermined pulse width by inputting the input signal. 2. The semiconductor memory device according to claim 1, wherein said control signal generating means can track a word line delay inside a chip. The semiconductor memory device of claim 1, wherein a pulse width of the precharge and equalization control signals is at least 10 ns or more. 2. The apparatus of claim 1, wherein the control signal generating means amplifies the cell data output from the memory cell array and connects the sense amplifier controlled by the precharge and equalization control signals to the sense amplifier and buffers the output data. And a data output buffer.