KR100356795B1 - Sram having write driver circuit - Google Patents

Abstract

The SRAM according to the present invention includes write transfer means for switching write data loaded on a pair of write data bus lines to a bit line pair by a column decoder output signal, and read data loaded on the bit line pair to the column decoder output signal. A lead transmission means for switching to a lead data bus line pair by means of receiving the write data and the write enable signal, and during the read operation, precharges the pair of write data bus lines to a first voltage level, The control unit has no influence on the line pair, and during the write operation, the write driver transmits the write data to the cell simultaneously through the write data bus line pair and the read data bus line pair, and transmits the read data to the read data bus line pair. Detected data or read data Characterized in that it comprises a sense amplifier.

Description

SRAM with light driver circuit {SRAM HAVING WRITE DRIVER CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SRAM having a write driver, and more particularly, to an SRAM having an improved write operation by allowing a write driver used in a write operation to control a read data bus line. .

In general, a signal amplified by a sense amplifier in a row address path is loaded onto a data bus line by selection of a column select from a bit line, and then amplified back to a data bus line sense amplifier to read a path reaching the output buffer. The path from the data input buffer to the sense amplifier is called the write path and the two are called the data path.

1 is a configuration diagram of an SRAM showing read data bus lines rdb and rdbb and write data bus lines wdb and wdbb according to a conventional read / write operation.

As shown, the write driver 10 driving the write data input through the input pad by the write enable signal WE to the write data bus line pairs wdb and wdbb, and the write data bus during the write operation. Write transfer gates N1 and N2 for transferring the write data transferred to the line pairs wdb and wdbb to the bit line pairs BL and / BL by the column decoder output signal yd, and the bit lines during the read operation. Read transfer gates P1 and P2 for transferring read data carried on the pairs BL and / BL to the read data bus line pairs rdb and rdbb by the column decoder output signal ydb, and the read data bus lines. It consists of a sense amplifier 20 which senses and amplifies the read data transferred in pairs rdb and rdbb.

In the conventional SRAM circuit, data bus lines are divided into read data bus line pairs rdb and rdbb and write data bus line pairs wdb and wdbb to reduce the loading of data lines.

The read operation is performed through the read transfer gates P1 and P2 turned on by the output signal ydb of the column decoder when the cell data is loaded into the bit line pairs BL and / bl by the row address path. Data is delivered in read data busline pairs (rdb, rdbb). When read data is loaded on the read data bus line pairs rdb and rdbb, the sense amplifier enable signal SE is activated to drive the sense amplifier 20. At this time, the read data amplified by the sense amplifier 20 is transferred to the data output buffer through the read driver selected according to the bit system of the data output. The data output buffer is activated under the control of the output enable signal (/ OE) and the cascade (/ CAS) to output data to the outside.

In the write operation, the write data input through the input pad and the data input buffer are transferred to the write data busline pairs (wdb and wdbb) through the selected write driver. The write data transferred to the write data bus line pairs wdb and wdbb are transferred to the bit line pairs BL and / BL selected by the output signal yd of the column decoder and stored in the memory cell.

FIG. 2 is a circuit diagram of the write driver 10 shown in FIG. 1, and includes a first inverter INV1 for inputting a data signal and a second inverter for inverting an output signal of the first inverter INV1. INV2, a third inverter INV3 for inputting the write enable WE, a first NAND gate for inputting an output signal of the first inverter INV1 and an output signal of the third inverter INV3. NA1), a second NAND gate NA2 for inputting an output signal of the second inverter INV2, and an output signal of the third inverter INV3, the first NAND gate NA1, and a second NAND gate. Connected between the fourth inverter INV4 and the sixth inverter INV6 and the output node Nd1 of the fourth inverter INV4 and the write data bus line wdb respectively connected to the output terminal of NA2. The fifth inverter INV5 and the seventh inverter INV7 connected between the output node Nd2 of the sixth inverter INV6 and the write data bus line wdbb. do. In addition, a power supply voltage (8) is inputted to the write data bus lines wdb and wdbb by the eighth inverter INV8 for inputting the write enable bar signal / WE and the output signal of the eighth inverter INV8. Equalizing agent for equalizing the write data bus lines wdb and wdbb by the precharge third and fourth PMOS transistors P3 and P4 for supplying Vcc and the output signal of the eighth inverter INV8. A precharge and equalization circuit section 12 composed of five PMOS transistors P5 is provided.

3 shows an operation waveform of a conventional write driver circuit, where a is a write drive enable signal, a b is a bit line (BL), a c is a bit line bar (/ BL), and a d is a write data bus line (wdb) and symbol e denote a write data bus line bar (/ wdbb), respectively.

However, in the SRAM implemented by the conventional write driver circuit configured as described above, when the write driver 10 is enabled during the write operation, the write operation is performed to the cell only through the pair of write data bus lines wdb and wdbb. The read data bus line pairs rdb and rdbb are left in the pull-up disabled state. At this time, the read data bus line pairs rdb and rdbb act as a loading that the write driver 10 charges, thereby hindering the write operation, slowing down the operation speed and lowering stability. .

Accordingly, the present invention has been made to solve the above problems, and the present invention provides a write data bus line and a write data bus line when the write driver is enabled during the write operation of the SRAM divided into the read data bus line and the write data bus line. By simultaneously writing to the cell with the lead data bus line, the lead data line acts as a loading driven by the write driver, eliminating the problem of disturbing the light operation, and also writing through the read data bus to improve the operation speed. The purpose is to provide a possible SRAM.

1 is a configuration diagram of an SRAM showing a read data bus line and a write data bus line according to a conventional read / write operation.

FIG. 2 is a circuit diagram of the light driver shown in FIG.

3 is an operation waveform diagram of a conventional light driver circuit.

4 is a configuration diagram of an SRAM showing a read data bus line and a write data bus line according to the read / write operation of the present invention.

5 is a light driver circuit diagram according to the present invention.

6 is an operation waveform diagram of the light driver circuit of the present invention.

Explanation of symbols on the main parts of the drawings

10, 100: light driver 20: sense amplifier

30: column decoder

12: precharge and equalization circuit

120: first output driver 140: second output driver

In order to achieve the above object, the SRAM of the present invention,

Write transfer means for switching write data loaded on a pair of write data bus lines into a bit line pair by a column decoder output signal, and read data loaded on the bit line pair as a read data bus line pair by the column decoder output signal. Receiving means for switching for switching and receiving the write data and the write enable signal, during the read operation pre-charges the light data bus line pair to a first voltage level and has no effect on the lead data bus line pair And a light driver means for simultaneously driving the write data to the cell through the write data bus line pair and the read data bus line pair during a write operation, and write data or read data transferred to the read data bus line pair. Includes sense amplifier to detect and amplify Characterized in that comprised over.

Here, the light transmission means is characterized by consisting of an NMOS transistor.

The lead transfer means is characterized by consisting of a PMOS transistor.

The first voltage level may be a power supply voltage level.

The write driver means has no effect on the read data bus line pair during the read operation.

The write driver means inputs the write data signal and the write driver enable signal, respectively, and generates precharge voltages of the first voltage level in the disabled state by a logical combination, and in the disable operation in the read operation. The voltage level is maintained as it is, and during the write operation, the input data signal is driven and transmitted to the write data bus line pair and the read data bus line pair, respectively.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

FIG. 4 is a schematic diagram of an SRAM showing a read data bus line and a write data bus line according to the read / write operation of the present invention. The write data inputted through the input pad by the write enable signal WE is written into the write data. The write driver 100 driving the bus line pairs wdb and wdbb and the read data bus line pairs rdb and rdbb, respectively, and write data transferred to the write data bus line pairs wdb and wdbb, respectively. The read transfer gates N1 and N2 respectively transmit to the bit line pairs BL and / BL by the column decoder output signal yd and the read through the column decoder output signal ydb during the write and read operations. Read transfer gates P1 and P2 connecting the data bus line pairs rdb and rdbb to the bit line pairs BL and / bl, and the write or reads transferred to the read data bus line pairs rdb and rdbb. Data It consists of the sense amplifier 20 which senses and amplifies.

An operation of the SRAM implemented by the light driver circuit according to the present invention having the above configuration will be described.

First, in the read operation, when the cell data is loaded into the bit line pairs BL and / BL by the row address path, the read transfer transistors P1 and P2 turned on by the output signal ydb of the column decoder. Read data is transferred to read data bus line pairs rdb and rdbb. When read data is loaded on the read data bus line pairs rdb and rdbb, the sense amplifier enable signal SE is activated to drive the sense amplifier 20. At this time, the read data amplified by the sense amplifier 20 is transferred to the data output buffer through the read driver selected according to the bit system of the data output. The data output buffer is activated under the control of the output enable signal (/ OE) and the cascade (/ CAS) to output data to the outside.

In the write operation, the write data input through the input pad and the data input buffer are transferred to the write data bus line pairs (wdb and wdbb) and the read data bus line pairs (rdb and rdbb) through the selected write driver. The write data transferred to the write data bus line pairs (wdb and wdbb) and the lead data bus line pairs (rdb and rdbb) are transferred to the light transfer transistors (N1 and N2) turned on by the output signals (yd and ydb) of the column decoder. And transfer to the selected bit line pairs BL and / BL through the transfer transistors P1 and P2 for storage.

When the write driver enable signal WE is disabled, the write data bus line pairs wdb and wdbb are precharged to the power supply voltage Vdd. At this time, the write data bus line pairs wdb and wdbb precharged with the power supply voltage Vdd have no effect on the read data bus line pairs rdb and rdbb, and thus have no effect on the read operation. The reason is that the precharge of the write data bus line pairs (wdb, wdbb) affects the read data bus line pairs (rdb, rdbb) only through the light transfer gates (N1, N2), where the threshold voltage (Vt) This is because there is a voltage drop as much as there is no effect on the sense amplifier using a voltage difference of 0.5V or less near the power supply voltage Vdd.

If the read data bus line pairs rdb and rdbb are precharged during the read operation, a voltage difference is prevented between the read data bus line pairs rdb and rdbb by the cell, thereby preventing the read operation. Result.

As such, when the read is not interrupted, the read operation is not interrupted, and when the write is eliminated, the element that obstructs the write operation is eliminated and the effective write operation is performed, thereby reducing the light pulse width. Speed and stability can be improved.

FIG. 5 is a circuit diagram of the write driver 100 of FIG. 4, wherein the first inverter INV1 inputs a data signal and the second inverter inverts the output signal of the first inverter INV1. INV2, a third inverter INV3 for inputting the write enable WE, a first NAND gate for inputting an output signal of the first inverter INV1 and an output signal of the third inverter INV3. NA1), a second NAND gate NA2 for inputting an output signal of the second inverter INV2, and an output signal of the third inverter INV3, the first NAND gate NA1, and a second NAND gate. Connected between the fourth inverter INV4 and the sixth inverter INV6 and the output node Nd1 of the fourth inverter INV4 and the write data bus line wdb respectively connected to the output terminal of NA2. A seventh inverter INV7 connected between the fifth inverter INV5 and the output node Nd2 of the sixth inverter INV6 and the write data bus line wdbb. It is. The voltage level of the sixth PMOS transistor P6 which transfers the power supply voltage Vcc to the read data bus line rdbb according to the voltage level of the write data bus line wdb, and the voltage level of the second node Nd2. The first output driver 120 is composed of a third NMOS transistor (N3) for flowing the voltage level of the read data bus line (rdbb) to the ground voltage (Vss) and the write data bus line (wdbb) The seventh PMOS transistor P7, which transfers the power supply voltage Vcc to the read data bus line rdb at a voltage level, and the read data bus line rdb at the voltage level of the first node Nd1. The second output driver unit 14 is constituted by the fourth NMOS transistor N4 which flows the voltage level to the ground voltage Vss.

When the write driver enable signal WE is disabled, since the first node Nd1 and the second node Nd2 become 'low', the outputs of the fifth inverter INV5 and the seventh inverter INV7 are output. Are all high, and precharge the write data buslines (wdb and wdbb) to 'high', respectively. Thus, both the PMOS and NMOS transistors of the first output driver 120 and the second output driver 140 are turned off, so that the read data bus line pairs rdbb and rdb have no effect.

In the read operation, the precharge of the write data bus lines wdb and wdbb affects the read data bus lines rdb and rdbb only through the NMOS transistors N1 and N2 of the column transfer gate. The voltage drop by Vtn is generated so that the sense amplifier 20 using a voltage difference of 0.3 V or less near the power supply voltage Vcc is not affected. If the PMOS transistors and the NMOS transistors of the first output driver 120 and the second output driver 140 are not turned off, the read data bus lines rdb and rdbb may be precharged by the cell. Since the voltage difference is prevented from occurring between the read data bus lines rdb and rdbb, the read operation is interrupted.

In the write operation, the write data bus lines wdb and wdbb are written to the cell through the NMOS transistors N1 and N2 of the column transfer gate, and the read data bus lines rdb and rdbb are written to the first output driver 120. ) And the second output driver 140 to write to the cell through the column transfer gates P1 and P2.

As such, when the read is not interrupted, the read operation is not interrupted, and when the write is eliminated, the element that obstructs the write operation is eliminated and the effective write operation is performed, thereby reducing the light pulse width. Speed and stability can be improved.

6 shows an operating waveform of the write driver circuit of the present invention, where a is a write drive enable signal, a b is a bit line (BL), a c is a bit line bar (/ BL), and a d is a write data Bus line wdb and symbol e denote a write data bus line bar / wdbb, respectively.

An operation waveform according to the write driver circuit of the present invention will be described in comparison with the conventional waveform shown in FIG. Although the write data bus line (wdb) does not show a large difference between 0.05V and 0.01V, the bit line voltage directly affecting the cell shows that the write data busline (wdb) shows a large difference between 0.51V and 0.21V. If the bit line voltage is high during writing, the cell may not be written to the cells with poor cell characteristics. Therefore, by applying the structure of the present invention, defects due to cell characteristic variations can be reduced and high reliability can be obtained.

As described above, according to the SRAM according to the present invention, when the write driver is enabled during the operation of the SRAM in which the data bus line is divided into the read data bus line and the write data bus line, the write data bus line and the read data are enabled. By simultaneously writing to the cell with the bus line, the read data line acts as a loading driven by the write driver, eliminating the problem of disturbing the write operation, and also writing through the read data bus, thereby improving the operation speed. It works.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (7)

In a semiconductor memory device, Light transmission means for switching the write data carried on the pair of write data bus lines to the pair of bit lines by the column decoder output signal; Read transfer means for switching the read data carried in the bit line pair to a read data bus line pair by the column decoder output signal; Receiving the write data and the write enable signal, the light data bus line pair is precharged to a first voltage level during a read operation, and the read data bus line pair is controlled to have no effect. A light driver means for simultaneously driving the write data to the cell via the light data bus line pair and the lead data bus line pair; And a sense amplifier configured to sense and amplify write data or read data transferred to the read data bus line pair. The method of claim 1, And said light transmitting means comprises an NMOS transistor. The method of claim 1, And said lead transfer means is composed of a PMOS transistor. The method of claim 1, And the first voltage level is a power supply voltage level. The method of claim 1, And the write driver means has no effect on the read data bus line pair during the read operation. The method of claim 1, wherein the light driver means, The write data signal and the write driver enable signal are respectively input to generate a precharge voltage having a first voltage level in a disabled state by a logic combination, and maintain the voltage level in the disabled state in a read operation. During the write operation, the SRAM configured to drive and transmit the input data signal to the write data bus line pair and the read data bus line pair, respectively. The method of claim 6, wherein the light driver means, A first inverter INV1 for inputting a data signal, a second inverter INV2 for inverting an output signal of the first inverter INV1, and a third inverter for inputting a write enable WE; INV3, a first NAND gate NA1 for inputting an output signal of the first inverter INV1 and an output signal of the third inverter INV3, an output signal of the second inverter INV2, and the first signal. A third NAND gate NA2 for inputting an output signal of the third inverter INV3, a fourth inverter INV4 connected to output terminals of the first NAND gate NA1 and the second NAND gate NA2, and Output of the sixth inverter INV6, the fifth inverter INV5 connected between the output node Nd1 of the fourth inverter INV4 and the write data bus line wdb, and the output of the sixth inverter INV6. The power supply is turned on by the voltage level of the seventh inverter INV7 connected between the node Nd2 and the write data bus line wdbb and the write data bus line wdb. The voltage level of the read data bus line rdbb is determined by the voltage level of the sixth PMOS transistor P6 that transfers Vcc to the read data bus line rdbb and the second node Nd2. The first data driver 120 including the third NMOS transistor N3 flowing through Vss) and the power supply voltage Vcc by the voltage level of the write data bus line wdbb and the read data bus line rdb. A fourth NMOS transistor N4 for flowing the voltage level of the read data bus line rdb to the ground voltage Vss based on the seventh PMOS transistor P7 and the voltage level of the first node Nd1. SRAM comprising a second output driver unit (14) consisting of.