KR940017195A

KR940017195A - Binary increment circuit

Info

Publication number: KR940017195A
Application number: KR1019920026874A
Authority: KR
Inventors: 김성곤
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1992-12-30
Filing date: 1992-12-30
Publication date: 1994-07-26
Also published as: KR950006351B1

Abstract

본 발명은 바이너리 데이타를 필요로 하는 경우 현재의 값에서 '1'씩 증가시키는 고속증가 회로에 관한 것으로, 특히 바이너리 데이타를 처리하는 및 프로그램 카운터 등에 적용되는 바이너리 증가 회로에 관한 것으로, 짝수번째 데이타를 인가받는 반전 버퍼(40), 상기 반전 버퍼(40)를 통해 입력된 데이타를 가산한 후 다음 비트의 입력이 되도록 하는 제1반분 가산수단(80), 상기 제1반분 가산수단(80)에 연결되는 제1출력버퍼(120), 상기 제1출력 버퍼(120)의 출력값을 일입력단으로 인가받고 타입력단으로는 rd_b(신호 명칭 부가요)신호를 인가받아 오버플로우 신호를 발생하기 위한 비반전 버퍼(30), 상기 비반전 버퍼(30)를 통해 입력된 데이타를 반분 가산한 출력값을 다음 비트의 입력이 되도록 하는 제2반분 가산수단(70), 상기 제2반분 가산수단(70)에 연결되는 제2출력버퍼(110), 상기 제2출력버퍼(110)의 출력값을 일입력단으로 인가받고 타입력단으로는 rd_b신호를 인가받아 오버플로우 신호를 발생하기 위한 제2오버플로우 신호 발생수단(7)으로 구성되는 홀수 번째 비트 라인을 구비하는 것을 특징으로 한다.The present invention relates to a fast increment circuit for increasing binary data by '1' from a current value when binary data is required, and more particularly to a binary increment circuit for processing binary data and applied to a program counter. An inversion buffer 40 to be applied, a first half addition means 80 for adding data input through the inversion buffer 40 and then inputting the next bit, and a connection to the first half addition means 80; A non-inverting buffer for generating an overflow signal by receiving an output value of the first output buffer 120 and the first output buffer 120 as one input terminal and receiving an rd_b (signal name addition request) signal as a type force terminal. 30 is connected to the second half adding means 70 and the second half adding means 70 for outputting the output value obtained by adding half the data input through the non-inverting buffer 30 to the next bit. Second overflow signal generating means 7 for generating an overflow signal by receiving the output value of the second output buffer 110 and the second output buffer 110 as one input terminal and receiving the rd_b signal as the type force terminal. And an odd-numbered bit line.

Description

Binary increment circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 상세 회로도.2 is a detailed circuit diagram according to the present invention.

Claims

An inversion buffer 40 receiving the even-numbered data, a first half addition means 80 for adding the data input through the inversion buffer 40 and then inputting the next bit, and the first half addition means ( A first overflow signal for generating an overflow signal by receiving an output value of the first output buffer 120 and the first output buffer 120 connected to the input terminal 80 and an rd_b signal to the type force terminal An even-numbered bit line consisting of the generating means 8, a non-inverting buffer 30 to which odd-numbered data is applied, and an output value obtained by adding half the data input through the non-inverting buffer 30 to the next bit input The second half adding means 70, the second output buffer 110 connected to the second half adding means 70, and the output value of the second output buffer 110 are applied to one input terminal and are connected to the type force stage. Generates an overflow signal by receiving the rd_b signal Second overflow in that it comprises an odd-numbered bit line consisting of the signal generating means (7) increases, characterized in binary circuit for.

The method according to claim 1, wherein said half adding means (80); A binary increment circuit comprising an exclusive OR gate and a NOR gate.

The method according to claim 1, wherein said half adding means (70); A binary increment circuit comprising an exclusive OR gate and a NAND gate.

※ Note: The disclosure is based on the initial application.