KR970055381A - D type flip-flop circuit - Google Patents

D type flip-flop circuit Download PDF

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Publication number
KR970055381A
KR970055381A KR1019950065854A KR19950065854A KR970055381A KR 970055381 A KR970055381 A KR 970055381A KR 1019950065854 A KR1019950065854 A KR 1019950065854A KR 19950065854 A KR19950065854 A KR 19950065854A KR 970055381 A KR970055381 A KR 970055381A
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KR
South Korea
Prior art keywords
data
gate
type flip
logic circuit
clock
Prior art date
Application number
KR1019950065854A
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Korean (ko)
Inventor
박민철
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950065854A priority Critical patent/KR970055381A/en
Publication of KR970055381A publication Critical patent/KR970055381A/en

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Abstract

본 발명은 D 타입 플립플롭 회로에 관한 것으로, 종래와 다른 회로 구성으로 플립플롭의 기능을 수행하도록 하는 D 타입 플립플롭 회로에 관한 것이다.The present invention relates to a D-type flip-flop circuit, and to a D-type flip-flop circuit to perform the function of the flip-flop in a circuit configuration different from the conventional.

종래의 D 타입 플립플롭 회로는 각 게이트간을 접속하기 위한 라인의 결선이 복잡하여 회로 집적도가 저하되는 문제점이 있다.Conventional D-type flip-flop circuits have a problem in that circuit integration is reduced due to complicated wiring of lines for connecting the gates.

본 발명은 앤드게이트와 배타적 논리합 게이트로 회로를 구성하여 D 타입 플립플롭의 기능을 수행함으로써 각 게이트간의 라인 결선을 단순화 시킬 수 있어 회로 집적도를 향상시키게 된다.According to the present invention, a circuit is formed of an AND gate and an exclusive OR gate to perform a D-type flip-flop function, thereby simplifying line connection between gates, thereby improving circuit integration.

Description

D 타입 플립플롭 회로D type flip-flop circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 D 타입 플립플롭 회로의 구성도.2 is a block diagram of a D-type flip-flop circuit according to the present invention.

Claims (3)

D 타입 플립플롭 회로에 있어서, 인가받은 데이타를 크럭에 따라 논리연산 처리하여 출력하는 제1논리회로와; 상기 제1논리회로로부터 인가받은 데이타를 클럭에 따라 논리연산 처리하여 출력하는 제2논리회로를 포함하는 것을 특징으로 하는 D 타입 플립플롭 회로.A D type flip-flop circuit, comprising: a first logic circuit for performing logic operation processing on an applied data according to a clock; And a second logic circuit configured to logically process and output data applied from the first logic circuit according to a clock. 제1항에 있어서, 상기 제1논리회로는 인가받은 데이타와 인가받은 반전된 클럭을 논리곱하여 생성된 데이타를 출력하는 제1앤드게이트와; 인가받은 클럭과 인가받은 귀환 데이타를 논리곱하여 출력하는 제2앤드게이트와; 상기 제1앤드게이트와 제2앤드게이트로부터 인가되는 데이타를 배타적 논리합하여 상기 제2논리회로 측으로 출력함과 동시에 상기 제2앤드게이트측에 귀환 데이타로서 출력하는 제1배타적 논리합 게이트를 포함하는 것을 특징으로 하는 D 타입 플립플롭 회로.2. The apparatus of claim 1, wherein the first logic circuit comprises: a first end gate outputting data generated by ANDing an applied data and an applied inverted clock; A second and gate for performing an AND operation on the applied clock and the received feedback data; And a first exclusive OR gate which outputs the data applied from the first and second gates to the second logic circuit side and outputs the feedback data to the second AND gate side. D type flip-flop circuit. 제1항에 있어서, 상기 제2논리회로는 상기 제1논리회로로부터 인가되는 데이타와 인가받은 클럭을 논리곱하여 출력하는 제3앤드게이트와; 반전되어 인가되는 클럭과 인가되는 귀환 데이타를 논리곱하여 출력하는 제4앤드게이트와; 상기 제3앤드게이트와 상기 제4앤드게이트로부터 인가되는 데이타를 배타적 논리합하여 출력단을 통해 출력함을 동시에 상기 제4앤드게이트축에 귀환 데이타로서 출력하는 제2배타적 논리합 게이트를 포함하는 것을 특징으로 하는 D 타입 플립플롭 회로.2. The apparatus of claim 1, wherein the second logic circuit comprises: a third end gate for performing an AND operation on the data applied from the first logic circuit and an applied clock; A fourth end gate which inverts and outputs an applied clock and an applied feedback data; And a second exclusive OR gate configured to perform exclusive OR on the data applied from the third and fourth AND gates and output the data through an output terminal, and simultaneously output the feedback data to the fourth AND gate axis as feedback data. D type flip-flop circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950065854A 1995-12-29 1995-12-29 D type flip-flop circuit KR970055381A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950065854A KR970055381A (en) 1995-12-29 1995-12-29 D type flip-flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950065854A KR970055381A (en) 1995-12-29 1995-12-29 D type flip-flop circuit

Publications (1)

Publication Number Publication Date
KR970055381A true KR970055381A (en) 1997-07-31

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ID=66624227

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950065854A KR970055381A (en) 1995-12-29 1995-12-29 D type flip-flop circuit

Country Status (1)

Country Link
KR (1) KR970055381A (en)

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