KR960008595A - Fast loop adder - Google Patents

Fast loop adder Download PDF

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Publication number
KR960008595A
KR960008595A KR1019940020384A KR19940020384A KR960008595A KR 960008595 A KR960008595 A KR 960008595A KR 1019940020384 A KR1019940020384 A KR 1019940020384A KR 19940020384 A KR19940020384 A KR 19940020384A KR 960008595 A KR960008595 A KR 960008595A
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KR
South Korea
Prior art keywords
adder
input
loop adder
loop
value
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Application number
KR1019940020384A
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Korean (ko)
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KR100348785B1 (en
Inventor
김진경
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이헌조
엘지전자 주식회사
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Priority to KR1019940020384A priority Critical patent/KR100348785B1/en
Publication of KR960008595A publication Critical patent/KR960008595A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

본 발명은 가산기의 속도제한에 의한 루프 가산기(Loop Adder)의 처리속도를 높이기 위한 고속 루프 가산기에 관한 것이다.The present invention relates to a high speed loop adder for increasing the processing speed of a loop adder by the speed limiter of the adder.

일반적으로 루프 가산기의 동작 속도는 수로 가산기의 처리속도에 의해 제한되므로 가산기를 구성하는 소자나 구성방법에 제한이 있을 경우 그 속도보다 싸른 루프 가산기의 구현은 불가능하였다. 따라서 본 발명은 가산기의 속도제한에 의한 루프 가산기의 처리속도를 향상시키기 위하여 가산기보다 처리속도가 빠른 복수개의 소루프 가산기로써 전체 루프 가산기를 구성함으로써 루프 가산기의 일구성요소인 가산기의 처리속도 이상의 루프 가산기를 얻을 수 있도록 한 것이다.In general, since the operation speed of the loop adder is limited by the processing speed of the channel adder, it is impossible to implement a loop adder that is faster than the speed when there is a limit in the element or method of constructing the adder. Therefore, in order to improve the processing speed of the loop adder due to the speed limiter of the adder, the present invention constitutes the entire loop adder with a plurality of small loop adders having a faster processing speed than the adder. I was able to get an adder.

Description

고속 루프 가산기Fast loop adder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 고속 루프 가산기의 블럭 구성도.3 is a block diagram of a fast loop adder according to the present invention.

제4도는 본 발명의 병렬 확장도.4 is a parallel expansion of the present invention.

Claims (4)

입력비트의 상위 1/2비트가 입력되어 딜레이되는 딜레이부와, 상기 입력비트의 하위 1/2비트가 일측 입력단에 입력되어 타측 입력단에 입력되는 값과 가산되며 가산결과가 1클럭 딜레이된 신호와 가산결과의 캐리를 출력하는 제1소루프 가산기와, 상기 딜레이부의 출력이 일측 입력단에 입력되어 타축 입력단에 입력되는 값과 상기 제1소루프 가산기의 캐리출력이 1클럭 딜레이된 신호가 가산되어 출력되는 제2소루프 가산기로 구성됨을 특징으로 하는 고속 루프 가산기.A delay unit in which an upper half bit of an input bit is input and delayed, a lower half bit of the input bit is input to one input terminal and added to a value input to the other input terminal, and an addition result is delayed by one clock delay; A first small loop adder for outputting a carry result of the addition result, a value at which the output of the delay unit is input to one input terminal, a value input to the other shaft input terminal, and a signal of one clock delay of the carry output of the first small loop adder are added and output. A high speed loop adder comprising: a second small loop adder. 제1항에 있어서, 상기 딜레이부는 레지스터임을 특징으로 하는 고속 루프 가산기.The fast loop adder of claim 1, wherein the delay unit is a register. 제1항에 있어서, 상기 제1루프 가산기의 타측 입력단에 입력되는 값은 제1루프 가산기의 가산 결과가 1클럭 딜레이된 값임을 특징으로 하는 고속 루프 가산기.The fast loop adder of claim 1, wherein a value input to the other input terminal of the first loop adder is a value in which an addition result of the first loop adder is delayed by one clock. 제1항에 있어서, 상기 제2루프 가산기의 타측 입력단에 입력되는 값은 제2루프 가산기의 가산 결과가 1클럭 딜레이된 값임을 특징으로 하는 고속 루프 가산기.The fast loop adder of claim 1, wherein a value input to the other input terminal of the second loop adder is a value in which an addition result of the second loop adder is delayed by one clock. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940020384A 1994-08-18 1994-08-18 High speed loop adder KR100348785B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940020384A KR100348785B1 (en) 1994-08-18 1994-08-18 High speed loop adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940020384A KR100348785B1 (en) 1994-08-18 1994-08-18 High speed loop adder

Publications (2)

Publication Number Publication Date
KR960008595A true KR960008595A (en) 1996-03-22
KR100348785B1 KR100348785B1 (en) 2002-12-11

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Application Number Title Priority Date Filing Date
KR1019940020384A KR100348785B1 (en) 1994-08-18 1994-08-18 High speed loop adder

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KR100348785B1 (en) 2002-12-11

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