KR960008595A - Fast loop adder - Google Patents
Fast loop adder Download PDFInfo
- Publication number
- KR960008595A KR960008595A KR1019940020384A KR19940020384A KR960008595A KR 960008595 A KR960008595 A KR 960008595A KR 1019940020384 A KR1019940020384 A KR 1019940020384A KR 19940020384 A KR19940020384 A KR 19940020384A KR 960008595 A KR960008595 A KR 960008595A
- Authority
- KR
- South Korea
- Prior art keywords
- adder
- input
- loop adder
- loop
- value
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
본 발명은 가산기의 속도제한에 의한 루프 가산기(Loop Adder)의 처리속도를 높이기 위한 고속 루프 가산기에 관한 것이다.The present invention relates to a high speed loop adder for increasing the processing speed of a loop adder by the speed limiter of the adder.
일반적으로 루프 가산기의 동작 속도는 수로 가산기의 처리속도에 의해 제한되므로 가산기를 구성하는 소자나 구성방법에 제한이 있을 경우 그 속도보다 싸른 루프 가산기의 구현은 불가능하였다. 따라서 본 발명은 가산기의 속도제한에 의한 루프 가산기의 처리속도를 향상시키기 위하여 가산기보다 처리속도가 빠른 복수개의 소루프 가산기로써 전체 루프 가산기를 구성함으로써 루프 가산기의 일구성요소인 가산기의 처리속도 이상의 루프 가산기를 얻을 수 있도록 한 것이다.In general, since the operation speed of the loop adder is limited by the processing speed of the channel adder, it is impossible to implement a loop adder that is faster than the speed when there is a limit in the element or method of constructing the adder. Therefore, in order to improve the processing speed of the loop adder due to the speed limiter of the adder, the present invention constitutes the entire loop adder with a plurality of small loop adders having a faster processing speed than the adder. I was able to get an adder.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명에 따른 고속 루프 가산기의 블럭 구성도.3 is a block diagram of a fast loop adder according to the present invention.
제4도는 본 발명의 병렬 확장도.4 is a parallel expansion of the present invention.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940020384A KR100348785B1 (en) | 1994-08-18 | 1994-08-18 | High speed loop adder |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940020384A KR100348785B1 (en) | 1994-08-18 | 1994-08-18 | High speed loop adder |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960008595A true KR960008595A (en) | 1996-03-22 |
KR100348785B1 KR100348785B1 (en) | 2002-12-11 |
Family
ID=37488913
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940020384A KR100348785B1 (en) | 1994-08-18 | 1994-08-18 | High speed loop adder |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100348785B1 (en) |
-
1994
- 1994-08-18 KR KR1019940020384A patent/KR100348785B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100348785B1 (en) | 2002-12-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR900005264A (en) | Clock Signal Switching Circuit and Its Switching Method | |
KR850003479A (en) | Semiconductor integrated circuit | |
KR920022677A (en) | Frequency multiplier | |
KR920015738A (en) | Addition circuit | |
KR960008595A (en) | Fast loop adder | |
KR970013725A (en) | Glitch Rejection Circuit Using Time Delay | |
RU2007032C1 (en) | Device which produces members of multiplicative groups of galois fields gf(p) | |
KR950024431A (en) | Address input circuit of static RAM | |
KR950033802A (en) | Synchronous counter and its carry propagation method | |
KR960001978A (en) | Barrel shifter circuit | |
KR950007531A (en) | 2-D digital filter | |
KR930018844A (en) | Shift clock generation circuit for adjusting the interval of shift signal | |
KR100197529B1 (en) | Data compression circuit using pass transistor multiplex | |
KR940017211A (en) | Sample doubler | |
KR940017195A (en) | Binary increment circuit | |
KR940010792A (en) | Clock multiplexing circuit | |
KR940012119A (en) | ARMA filter suitable for high speed processing | |
KR970022730A (en) | High speed addition circuit | |
KR970019079A (en) | Clock Buffer Circuit | |
KR970063922A (en) | Bandwidth tunable loop filter | |
KR890010690A (en) | Multiplier Circuit Using Full Adder | |
KR970055594A (en) | Logic decoding circuit in PPM communication method | |
KR940015890A (en) | Digit Serial Multiplexer | |
KR970053948A (en) | Expansion block circuit to extend the width of asynchronous input pulses | |
KR970049445A (en) | Multibit Adder in Digital Signal Processor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
E902 | Notification of reason for refusal | ||
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20050607 Year of fee payment: 4 |
|
LAPS | Lapse due to unpaid annual fee |