KR890010690A - Multiplier Circuit Using Full Adder - Google Patents

Multiplier Circuit Using Full Adder Download PDF

Info

Publication number
KR890010690A
KR890010690A KR870014636A KR870014636A KR890010690A KR 890010690 A KR890010690 A KR 890010690A KR 870014636 A KR870014636 A KR 870014636A KR 870014636 A KR870014636 A KR 870014636A KR 890010690 A KR890010690 A KR 890010690A
Authority
KR
South Korea
Prior art keywords
multiplier circuit
full adder
output
adder
full
Prior art date
Application number
KR870014636A
Other languages
Korean (ko)
Inventor
전익범
Original Assignee
안시환
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 안시환, 삼성전자 주식회사 filed Critical 안시환
Priority to KR870014636A priority Critical patent/KR890010690A/en
Publication of KR890010690A publication Critical patent/KR890010690A/en

Links

Abstract

내용 없음No content

Description

전 가산기를 이용한 승수회로Multiplier Circuit Using Full Adder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는, 본 발명의 회로도.2 is a circuit diagram of the present invention.

Claims (1)

X1과 Y1을 입력시켜 앤드게이트(A1)의 출력 Z1에서는 첫째 비트를 얻도록 구성하고, X1Y2, X2와 Y1, X1과 Y3, X2와 Y2, X3와 Y1, X1과 Y4, X2와 Y3, X3와 Y2, X4와 Y1을 앤드게에트(A2-A9)에 각각 입력시켜서 앤드게이트(A2-A9)의 출력을 전 가산기(FA1-FA6)에 입력하여 전 가산기(FA1-FA6)의 출력Z2-Z4에서는 출력의 값을 얻을수 있도록 구성함을 특징으로 하는 전 가산기를 이용한 승수회로.Input X 1 and Y 1 to configure the first bit in output Z 1 of AND gate (A 1 ), and X 1 Y 2 , X 2 and Y 1 , X 1 and Y 3 , X 2 and Y 2 , X 3 and Y 1, X 1 and Y 4, X 2 and Y 3, an X 3 and Y 2, X 4 and Y 1 by the respective input-and-eth- to (a 2 -A 9) aND gates (a 2 - by entering the output of the a 9) in the full-adder (FA 1 -FA 6) in the output Z 2 -Z 4 of the full adder (FA 1 -FA 6) a full-adder, it characterized in that the configuration to get the value of the output Multiplier circuit used. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR870014636A 1987-12-21 1987-12-21 Multiplier Circuit Using Full Adder KR890010690A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR870014636A KR890010690A (en) 1987-12-21 1987-12-21 Multiplier Circuit Using Full Adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR870014636A KR890010690A (en) 1987-12-21 1987-12-21 Multiplier Circuit Using Full Adder

Publications (1)

Publication Number Publication Date
KR890010690A true KR890010690A (en) 1989-08-10

Family

ID=68459601

Family Applications (1)

Application Number Title Priority Date Filing Date
KR870014636A KR890010690A (en) 1987-12-21 1987-12-21 Multiplier Circuit Using Full Adder

Country Status (1)

Country Link
KR (1) KR890010690A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11500629B2 (en) 2020-01-07 2022-11-15 SK Hynix Inc. Processing-in-memory (PIM) system including multiplying-and-accumulating (MAC) circuit
US11513733B2 (en) 2020-01-07 2022-11-29 SK Hynix Inc. Processing-in-memory (PIM) system and operating methods of the PIM system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11500629B2 (en) 2020-01-07 2022-11-15 SK Hynix Inc. Processing-in-memory (PIM) system including multiplying-and-accumulating (MAC) circuit
US11513733B2 (en) 2020-01-07 2022-11-29 SK Hynix Inc. Processing-in-memory (PIM) system and operating methods of the PIM system

Similar Documents

Publication Publication Date Title
KR900013388A (en) Multiplier Circuit Using Neural Network
KR900013516A (en) Associative Memory Using Wired Network
KR830009695A (en) Arbitration Circuit
KR890011209A (en) Due slope waveform generator
KR840000114A (en) Phase comparator
KR930001572A (en) Voltage-to-Current Converter for Active Filters Used in Noise Reduction Circuits
KR890010690A (en) Multiplier Circuit Using Full Adder
KR880001131A (en) Output buffer circuit
KR910009107A (en) Color signal enhancer
KR870006395A (en) electronic scale
KR920010616A (en) Chip Enable Detection Circuit
KR900003725A (en) Input Circuits Performing Test Mode Functions
KR920013918A (en) How to Configure Key Matrix Using Multiple Contacts
KR890015500A (en) Integration delay circuit
KR830009697A (en) Dynamic Dividers Using Shift Registers
KR850005074A (en) Electronic lock without KEY
KR930017314A (en) Address decoding method and circuit
KR900016857A (en) Clear blue circuit
JPS56155444A (en) Large scale integrated circuit device
KR900002162A (en) Bidirectional I / O Buffer Circuit
KR900013721A (en) TTL NAND-Gake for Improved Latency
KR890008717A (en) Square computing unit
KR890011170A (en) Bicy MOS inverter circuit
KR870006507A (en) Display of binary value below decimal point
KR940015792A (en) High speed addition circuit

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application