JPS56155444A - Large scale integrated circuit device - Google Patents

Large scale integrated circuit device

Info

Publication number
JPS56155444A
JPS56155444A JP5901880A JP5901880A JPS56155444A JP S56155444 A JPS56155444 A JP S56155444A JP 5901880 A JP5901880 A JP 5901880A JP 5901880 A JP5901880 A JP 5901880A JP S56155444 A JPS56155444 A JP S56155444A
Authority
JP
Japan
Prior art keywords
data
gate
input terminal
carry
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5901880A
Other languages
Japanese (ja)
Other versions
JPS6116093B2 (en
Inventor
Osamu Nishijima
Makoto Yamatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP5901880A priority Critical patent/JPS56155444A/en
Publication of JPS56155444A publication Critical patent/JPS56155444A/en
Publication of JPS6116093B2 publication Critical patent/JPS6116093B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To add a shift function including series input and output by the addition of a minimum of circuits. CONSTITUTION:A shift function is provided simply by adding two gates, an AND gate 23 and an OR gate 24. Namely, the shift operation is executed by adding signals to terminals 27-31, outputting the data of a data register 19 to data buses 21, 22, further, applying the data input to be applied to a data input terminal 25 to the carry-borrow input terminal of an arithmetic unit ALU18 by the use of an AND gate 23 and an OR gate 24, performing the binary full addition of the data outputted to the data buses, and the data to be applied to the carry-borrow input terminal and inputting the results to the data register 19 and a carry memory 20.
JP5901880A 1980-05-02 1980-05-02 Large scale integrated circuit device Granted JPS56155444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5901880A JPS56155444A (en) 1980-05-02 1980-05-02 Large scale integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5901880A JPS56155444A (en) 1980-05-02 1980-05-02 Large scale integrated circuit device

Publications (2)

Publication Number Publication Date
JPS56155444A true JPS56155444A (en) 1981-12-01
JPS6116093B2 JPS6116093B2 (en) 1986-04-28

Family

ID=13101122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5901880A Granted JPS56155444A (en) 1980-05-02 1980-05-02 Large scale integrated circuit device

Country Status (1)

Country Link
JP (1) JPS56155444A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05143285A (en) * 1991-11-20 1993-06-11 Matsushita Electric Ind Co Ltd Arithmetic unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05143285A (en) * 1991-11-20 1993-06-11 Matsushita Electric Ind Co Ltd Arithmetic unit

Also Published As

Publication number Publication date
JPS6116093B2 (en) 1986-04-28

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