JPS56135251A - Integrated logic circuit device - Google Patents
Integrated logic circuit deviceInfo
- Publication number
- JPS56135251A JPS56135251A JP3798880A JP3798880A JPS56135251A JP S56135251 A JPS56135251 A JP S56135251A JP 3798880 A JP3798880 A JP 3798880A JP 3798880 A JP3798880 A JP 3798880A JP S56135251 A JPS56135251 A JP S56135251A
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- outputs
- integrated logic
- gate
- same functions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1608—Error detection by comparing the output signals of redundant hardware
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To perform IC-implementation efficiently by facilitating a doubled comparison check by applying a common input to two integrated logic circuits having exactly the same functions and by outputting an error signal from an OR gate by detecting their outputs. CONSTITUTION:Integrated logic circuits 1 and 1', having exactly the same functions, are applied with common input signal 2 to put the same functions in operation simultaneously. Outputs of internal logic circuits of circuits 1 and 1' are sent to output circuits 5 and 6, and 5' and 6'; outputs B of those output circuits are sent to terminals 3a...3n, and 3a'...3n', and outputs C to OR gates 7 and 7'. Outputs of those gates 7 and 7' are inputted to OR gate 9 via error detecting circuits 8 and 8' of circuits 1 and 1' and from gate 9, error signal 10 is outputted. Consequently, a doubled comparison check is made nearly without increasing hardware and electric power consumption, and the integration is done efficiently.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3798880A JPS56135251A (en) | 1980-03-25 | 1980-03-25 | Integrated logic circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3798880A JPS56135251A (en) | 1980-03-25 | 1980-03-25 | Integrated logic circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56135251A true JPS56135251A (en) | 1981-10-22 |
Family
ID=12512941
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3798880A Pending JPS56135251A (en) | 1980-03-25 | 1980-03-25 | Integrated logic circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56135251A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61169015A (en) * | 1985-01-23 | 1986-07-30 | Hitachi Ltd | Flip-flop circuit |
-
1980
- 1980-03-25 JP JP3798880A patent/JPS56135251A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61169015A (en) * | 1985-01-23 | 1986-07-30 | Hitachi Ltd | Flip-flop circuit |
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