JPS61169015A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To decrease remarkably errors in software by providing two elements each constituting a feedback loop, connecting inputs together and ORing output signals to provide a withstanding performance against an alpha ray. CONSTITUTION:A circuit 1 forming the feedback loop is a required minimum unit to store information and called a latch. An FF circuit comprising an input control circuit 2 applying input signals VIN1, VIN2 to the latch 1 and an output control circuit 3 controlling output signals VOUT1, VOUT2 from the latch 1 is duplicated in the elements causing an error so that no soft error is caused because of an alpha ray or the like. Thus, the software error is decreased remarkably while minimizing the increase in the number of elements due to duplication.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a flip-flop circuit for temporarily storing information in a logic device, and in particular to a flip-flop circuit for temporarily storing information in a logic device. This invention relates to a flip-flop circuit that is improved so that soft errors do not occur due to wires, etc.

[Background of the invention]

FIG. 19 shows an example of the logical configuration of a flip-flop circuit. When the clock input 62 applied through the input terminal In is in the "1" state, the clock input 62 is applied through the input terminal In1. It has a function of outputting the contents of the data input 61 to the positive output terminal 64 and outputting the inverted contents of the data input 61 to the negative output terminal 63, and when the clock input 62 is in the "O" state, Clock input 62 before
It has a function of storing the contents of the data input 61 when the value is 1'', and outputting the stored contents to the positive side output terminal 64 and the inverted version of the stored contents to the negative side output terminal 63. In addition, in the figure, 69A is an inverter, 66
A to 66G are OR gates, 67 is an AND gate, and 65 is a feedback line.

FIG. 20 is a conventional circuit configuration diagram for realizing the flip-flop shown in FIG. 19. This circuit uses an emitter coupled logic circuit (Emitter Coup) as a basic gate.
LED Logic (hereinafter referred to as ECL circuit) is used, and one gate is configured for each of the constant current sources 718, 728 and 738. Focusing on the gate corresponding to the constant current source 718, the input terminal of this gate is the transistor 71↓.

712, and the NOR and OR outputs are obtained from the common collectors of transistors 711 and 712 and the collector of transistor 713, respectively. The same applies to other gates.

Next, referring to FIG. 20, the operation corresponding to the AND gate 67 of FIG. 19 will be explained. In the circuit of FIG. 20, the OR output of each of the three gates is obtained from the collectors of the transistors 713, 723, and 733 as described above, but in this circuit, the three collectors are commonly connected (703). and is output to 64 via emitter follower transistor 701. By connection 703, the OR outputs of the three gates are logically ANDed. On the other hand, the NOR output of each gate is an emitter follower.
It is output through transistors 714, 724, and 734, but the emitters of these transistors are commonly connected (
704), the NOR outputs of the three gates are logically ORed. This is equivalent to negating the AND of the OR output according to De Morgan's theorem. Therefore, with the circuit configuration of FIG. 20, the positive side output 64. A negative output 63 is obtained. For details of the circuits shown in FIGS. 19 and 20, see Japanese Patent Application No. 57-81426.

By the way, in recent years, alpha rays emitted from trace amounts of radioactive substances in semiconductor packaging materials have been causing damage.

It has become clear that memory and flip-flop circuits cause soft errors. FIG. 21 shows the situation when α rays are incident on a semiconductor chip, and shows the case of a bipolar transistor. 126, 127,
129 are the emitter, base, and collector regions, respectively, and 130 is the depletion layer of the PN junction formed by the collector 129 and the substrate 131. When 6α rays are incident, electron-hole pairs are generated along the trajectory 120. . Among the electron-hole pairs generated in each region, the electron-hole pairs generated in the depletion layer 130 and the substrate 131 have the greatest influence on circuit operation. Focusing on electrons, the electrons generated in the depletion layer 130 are attracted to the collector and collected by the electric field of the PN junction. Further, electrons generated in the substrate 131 reach the depletion layer 130 by diffusion and are then collected in the collector as above. Therefore, the influence of the incident α rays appears as current noise, and the current flows from the collector of the transistor into which the α rays are incident to the substrate.

Since the above properties relate to bipolar transistors, the situation is the same for memory and logic LSIs. For example, reports on soft errors related to bipolar memory can be found in Trans, IE, Transactions of the Institute of Electronics and Communication Engineers.
CE, Vol63-C, Na2 (1980-2)
(Sales, etc.; "Soft error in high-speed bipolar RAM due to α particles"), on the other hand, logic LSI
There have been no reports of soft errors occurring in logic LSIs.This is because logic LSIs require more circuit current and have larger signal amplitudes than memory LSIs. however.

In the future, as devices become smaller and more sophisticated, parasitic capacitance will decrease, so the amount of stored charge will also decrease, and soft errors will become a problem even in logic LSIs.

Furthermore, as a problem unique to logic LSIs, since the number of signal pins is large, CCB (
Controlled Co11apse Bondi
A chip connection method called ng) is being adopted (
For example, IEEE J, 5tate C1rcui
t, Vol S C-14, Ha5, pp818-8
22 (1979-11)).

In this method, solder balls are placed over the entire surface of the chip, but radioactive isotopes (eg, Ra, Am, etc.) contained as impurities in the solder can cause soft errors in the logic LSI. Since the solder balls are bonded to the chip, it is impossible to block the alpha rays by, for example, counterfeiting the chip with some material, and a circuit that is resistant to alpha rays is required.

The present inventors have previously filed an application for an α-resistant circuit for logic LSI (Japanese Patent Application No. 59-67653), which changes the reference potential of the circuit according to the current noise of α-rays. It applied a differential circuit.

Since differentiating circuits are quite dependent on the waveform of noise, they have not always been good in terms of stability of circuit operation.

[Purpose of the invention]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a flip-flop circuit that is resistant to radiation such as alpha rays and does not cause soft errors.

[Summary of the invention]

Therefore, in the present invention, the feedback signal is duplicated, that is, the conventional feedback signal is combined with an inverted signal of a signal obtained independently and in opposite phase to the conventional feedback signal.
It is a method that takes an OR logic with R logic or a separate signal of exactly the same phase and uses it as a feedback signal.In order for the feedback signal to cause an error from a logical high level to a low level, an OR logic is required. It is necessary for both of the two signals to cause an error, and since the probability of this error is extremely small, soft errors can be drastically reduced.

[Embodiments of the invention]

Before explaining the present invention, problems caused by alpha rays in flip-flop circuits will be explained in detail, taking a bipolar transistor as an example. FIG. 22 shows a current switching section of an ECL circuit, and shows how current noise due to α rays is expressed isometrically. This figure shows the case where α rays are incident on the transistor 223, and the noise source is 227. FIG. 23 shows what kind of fluctuations the noise caused by α rays causes in the signal level. 320 is, for example, the transistor 22 of FIG.
It shows the potential of the collector of No. 3, and the α-ray noise source 227
This causes noises such as 321 and 322.

The operation in which information in the flip-flop is lost due to this noise will be explained. As shown in FIG. 20, the feedback line 65 of the flip-flop runs from the collectors of the commonly connected transistors 713, 723, and 733, through the emitter follower transistor 701, and then to the bases of the transistors 722, 732, which are the input terminals of the gates. connected to. Therefore, transistor 713
When α rays are incident on either of ゜723.733.

The noise 321°32 shown in Fig. 23 is applied to the common collector.
2 occurs and is fed back. In that case, when the potential of the collector is at a low level, even if noise 321 occurs, the potential is only lowered further, so the LOW information of the flip-flop is not lost.On the other hand, when the potential of the collector is at a high level, the LOW information of the flip-flop is not lost. , when noise 322 is generated and fed back,
The feedback potential approaches the reference potentials v and m, and when the noise is large, the feedback potential, which should logically be at the High level, falls below VH, so E
The current in the CL circuit will switch and information will be lost.

The soft error mechanism caused by a drop in collector potential is similar not only in ECL circuits but also in other bipolar circuits, such as TTL (transistor-transistor logic) circuits.

Also in the case of field effect transistors (FETs).

Collector layer 129 of the bipolar transistor in FIG.
The source and drain of the FET correspond to this.

Similar error behavior occurs. That is, in the case of an N channel, a current flows from the drain to the substrate due to the incidence of α rays, and the drain potential decreases.

FIG. 1 is a schematic configuration diagram of the present invention. 1 is a circuit forming a feedback loop, and is the minimum necessary unit for storing information. Here, this unit is called a latch, and the input signal to latch 1 is V l ml t V
an input control circuit 2 for supplying l++2, etc.;
Output signal from latch 2 V e w t 1 yV,,
A circuit consisting of an output control circuit 3 for controlling t Among the elements constituting the feedback loop, the elements that cause errors are duplicated.

Simply duplicating each flip-flop doubles the number of flip-flops and requires an error determination circuit, which greatly increases the number of required circuits.

In the present invention, only the elements that cause information destruction are duplicated, and the duplicated signals are processed depending on the error mode that may occur. Therefore, while minimizing the increase in the number of elements due to duplication, it is possible to effectively drastically reduce soft errors.

FIG. 2 shows an example of the latch 1 used in the present invention. This figure shows the case of RS launch using a NOR circuit, and the RS
The operation of conventional circuits such as latches is explained, for example, in Yojibe Yokoi's ``Digital IC Practical Circuit Manual'' (Radio Gijutsu Sha). In FIG. 2, the portion added to the conventional circuit is the circuit within the broken line 20. NOR circuit 23.2 corresponds to NOR circuit 21.22.
It is doubled by 4. The NOR circuits 21 to 24 are
If the error mode from the logic high level to the low level occurs due to the incidence of α rays, the OR circuit 25
．． 26, no error signal is fed back. For example, when Q is High level, N
The outputs of the OR circuits 22 and 24 are at High level, but 1
Even if α rays enter the circuits 22 or 24, Q will not go to Low level unless the α rays enter one circuit 22 or 24 at the same time because of the OR circuit 26.

If the error mode is opposite to the above case, and the error goes from low level to high level, it is possible to prevent the duplicated signal from being used in an AND circuit as shown in FIG. In FIGS. 2 and 3, the gates constituting the latch are NOR, but the same applies to NAND.

FIG. 4 shows another example of the latch 1 shown in FIG. 1.

In this figure, an OR circuit 41 and an AND circuit 42 form a feedback loop. The portion added to the conventional circuit is the portion surrounded by a broken line 40.

In this embodiment, only the AND circuit 42 and the inverter 44 have an error mode from logic high level to low level.
1't"0Rti: Total, it is possible to replace the NAND circuit 43 and the inverter 44 with one AND circuit, but depending on the elements used, the configuration as in this example may be simpler. In the present invention, as in this embodiment, duplication only needs to be performed on gates that may cause errors, so that the increase in the number of elements due to duplication can be kept to a minimum.

In FIG. 5, a circuit 50 is added to prevent soft errors in the same latch as in FIG. 4, which is composed of an OR circuit 51 and an AND circuit 52.

As for the error mode, only the AND circuit 52 and the inverter 54 can cause an error from High level to Low level, as in FIG.

FIG. 6 is a block diagram of a D-type flip-flop using the latch shown in FIG. 4, and is characterized by the addition of a circuit 6o when compared with FIG. 19 of the conventional flip-flop. The input signals of this circuit 60 are the positive side output 64 and the negative side output 63 of this flip-flop circuit, and the negative side output 63 is inverted by the inverter circuit 69.

The two input signals to OR gate 68 are logically in phase. Therefore, in normal operation without the influence of alpha rays, the feedback signal 65 functions exactly the same as the original flip-flop shown in FIG. ' As a circuit configuration for realizing FIG. 6, the one shown in FIG. 7 can be considered. If we do the duplication at the transistor level, as shown here.

The increase in the number of elements due to duplication is extremely small. here,
Except for the circuit 70, this circuit has exactly the same configuration as the conventional flip-flop circuit shown in FIG. The inverter 69 in FIG.
This corresponds to 71 in FIG. Also, OR gate 6 in FIG.
8, in FIG. 7, the emitters of transistors 72 and 701 are connected (753), so logically O
R is taken. Similar to Figure 6, in Figure 7,
In normal operation without the influence of alpha rays, a single flip-flop circuit operates logically in exactly the same way as a conventional flip-flop circuit.

Next, in FIG. 7, the operation when α rays are incident will be explained. As mentioned above, the influence of α rays is caused by the transistor 71
When α rays are incident on the collector of either of No. 3, 723, and 733, the potential of that collector is lowered. Therefore, the common collector potential 703
One problem occurs when is logically at a high level. In other words, the logical High level becomes Low due to α-ray noise.
When it is lowered enough to be considered as w level, if it is fed back, the flip-flop will be reversed and information will be lost. In traditional flip-flops,
This reversal could not be avoided because the common collector potential 703 is fed back as is through the emitter follower. On the other hand, in the flip-flop of FIG. 7 according to this embodiment, the circuit 70 and the connection 73 provide
The feedback signal 65 is created by ORing the common collector potential 703 and the inverted signal of the negative output 63 of the latch6. Therefore, even if the common collector potential 703 logically changes from High level to Low level due to α-ray noise, , if the inverted signal of the negative side amount cuff 04 remains at the )1high level, the feedback signal 65 becomes High.
The level is maintained and the information in the latch circuit is not lost. Since the inverted signal 74 of the negative side amount cuff 04 is obtained from the common collector potential 703 and a separate transistor, the common collector potential 703 and the inverted signal 74 of the negative side amount cuff 04 are simultaneously changed from High level to Low by one α ray.
On the other hand, when the common collector potential 703 is at Low level, the negative side amount cuff 0
Since 4 is a high level, there is a risk that 704 will be lowered by α-ray noise. However, in this case, an error will not occur unless α rays are simultaneously incident on the negative side transistors of the current switch represented by constant current sources 728 and 738. The probability that α rays are simultaneously incident on the collector of 731 (or 732) is negligible. Therefore, soft errors in the latch circuit due to incidence of α rays become almost negligible.

FIG. 8 shows a method of configuring the circuit 70 in FIG.
This utilizes an ECL circuit that switches at 02.

FIG. 9 shows another method of configuring the circuit 70 in FIG. 7, in which a feedback signal 65 is obtained from the collector of a transistor 901 through an emitter follower.

In the above embodiment, the negative output 63 of the flip-flop is used as the input signal to the inverter 71. In other words, the OR connection of transistors 714°724.734 is used, but three new transistors are provided separately from these transistors, and each is connected in the same way as transistors 714°724.734 and input to the inverter 71. It is also possible to do so.

Further, in the above embodiment, the positive side output 64 of the latch is obtained by the same emitter follower transistor 701 as the feedback signal 65.

This can also be achieved with separate transistors. That is, like the transistor 701, the base is connected to the common collector 703 of the transistors 713, 723, and 733, and the positive output 64 is obtained from the emitter.

Another circuit configuration method for realizing FIG. 6 is shown in FIG. 10. In this circuit, constant current sources 718, 728, 73 are used instead of using the negative side capacitor 04 of the flip-flop as an input signal to the circuit 70 as shown in FIG.
By directly inputting the collector potential 11°12.13 on the negative side of the force rent switch represented by 8 as an input signal to the circuit 70, the feedback circuit speed can be increased. At this time, instead of the inverter 71, the NO
Use R gate 14. For this gate 14, the number of inputs of the circuits shown in FIGS. 8 and 9 can be increased to use circuits shown in FIGS. 11 and 12, respectively. That is, in FIG. 7, the ORing of the negative side outputs of each current switch and inversion in the circuit 71 is performed all together in the gate 14, so that the speed of one circuit can be increased. Also, NO
As an R gate, it is also possible to create a circuit as shown in Figure 13, which combines the stability achieved by using a constant current source as shown in Figure 11, and the high speed achieved by non-thresholding as shown in Figure 12. It is. Here, the division ratio of the resistors 335 and 336 is determined in consideration of speed increase and signal level. The capacitor 338 is a speed-up capacitor and can speed up the NOR output.

Although the negative side output of the latch is not shown in the circuit of FIG. 10, it can be similar to that of FIG. 7. Also, for the positive output 64, separate emitter follower transistors can be used for output and feedback, as described with reference to FIG.

Another embodiment of the present invention is shown in FIG. 14. In this embodiment,
Compared to the embodiment of FIG. 6, there is no OR gate 68, but instead an OR gate 66B.

If it is possible to increase the number of 66C inputs from 2 to 3, or increase the number of inputs by 6, then the circuit speed can be increased. The specific structure of each gate in FIG. 14 can be made in the same manner as in the embodiment shown in FIG. 6.

Still another embodiment of the present invention is shown in FIG.

This embodiment differs from the previous ones in that it is a vertically stacked EC.
This is a flip-flop using an L circuit, so-called series gate ECL, which has been made resistant to alpha rays. In FIG. 24 of the conventional circuit, data input crabs, 1. The mutual relationship between the clock phase input Imp, the positive output 64 of the latch, and the negative output 63 is exactly the same as in the case of FIG. To briefly explain the operation, when the clock phase input 1.2 is higher than the reference voltage v1.2, the data input 1.2 is higher than the reference voltage v1.2. , a current flows through one of the transistors of the transistor pair 551, 552. On the other hand, I m2 is the reference voltage V,
.

When it is lower, current flows through one of the transistors in transistor pair 553, 554 and data is retained. Feedback for holding data is fed back from the positive output 64 of the latch to the base of transistor 553.

An error can occur in this circuit due to the incidence of α rays when α rays enter the collectors of transistors 552 and 554 for producing the positive output 64.

Moreover, this is only when the output is at the Illight level.

Therefore, as shown in FIG. 15, for alpha ray resistance, transistors 566 and 567 are connected in parallel with transistors 552 and 554, respectively, but the collectors are separated and load resistors tL564 and 565 are connected separately. ,
A logical OR is obtained by a wired OR of emitter follower transistors 559 and 568, and a feedback signal is obtained.

By doing this, the transistor 552 (or 55
4) and 566 (or 567), soft errors will not occur unless α rays are incident on them.

In this embodiment, the series gate ECL circuit includes transistor pairs 553 and 554 for data retention.
Although the configuration is such that reference voltage v1.1 is applied to the bases of transistors 553 and 554, it is also possible to input signals having opposite phases to each other, that is, differential signals, to the bases of transistors 553 and 554. That is, the negative side output 63 can also be input to the base of the transistor 554. In this case, soft errors due to α rays can be prevented by performing duplication as shown in FIG. 15 in exactly the same way for the negative side output.

In addition, in this embodiment, the latch output and feedback signal are exactly the same, but as explained in the embodiment of FIG. 7, by connecting another emitter follower transistor, It is also possible to separate the output of the flip-flop and the feedback.

Still another embodiment of the present invention is shown in FIG.

This example is one of the circuit configurations for realizing FIG. 6, and is different from FIG.
This is a case where only R11l principle can be taken. Therefore, to obtain feedback 65, the negative output cuff 04 of the flip-flop is inverted by NOR gate 650. In this example, soft errors due to α rays are caused by gate 6.
This can occur when alpha rays are incident on the 50. therefore,
A single circuit using a circuit as shown in FIG. 17 as the gate 650 corresponds to FIG. No error will occur unless α rays are incident on the collectors 801 and 751 at the same time, so in reality, the α ray soft error will be very small.

In place of FIG. 17, duplication can be made in the same way as in FIGS. 9 and 13.

Until now, we have mainly shown examples of duplication at the transistor level for bipolar ECL circuits.
In addition to L, for example, TTL circuits can also be duplicated using the same concept. Figure 18 shows TTL
This is a duplication of the basic gate of , and when a flip-flop is constructed using this, the increase in the number of elements is smaller than duplication with gates. In FIG. 18, transistors 824, 827 . Diode 826. The resistor 829 is a duplicated part.

Also, unlike previous NPN transistors, PNP
In the case of a transistor, the circuit operation is essentially the same, except that the noise current due to α rays flows from the substrate to the collector. However, from Low level to H
In order to change the error mode to high level, the duplicated signals must be ANDed.

Furthermore, as mentioned at the beginning of the description of the embodiment, an N-channel FET is used in correspondence with the NPN transistor.

Corresponding to the PNP transistor, the P channel FET is α
Since the same circuit operation is shown for line noise, the concept of the embodiment using bipolar transistors described above can be applied as is.

〔Effect of the invention〕

As explained above, according to the present invention, a flip-flop circuit that does not impair normal latch operation, does not significantly increase the number of elements, is resistant to alpha rays, and does not cause soft errors. can be realized.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram of the present invention, FIGS. 2 to 18 are diagrams showing an embodiment of the present invention, and FIGS. 19 to 24 are diagrams showing conventional circuits. ■1.1. Vi,! ...Flip-flop circuit input signal. ■・11! v・wL2''° Output signal of flip-flop circuit, 1... Latch including a feedback loop with multiplexed elements, 2... Input control circuit, 3... Output control circuit, S... Set input, R...Reset input,
Q...affirmative output, Q-...negative output, 21-24...
・NOR gate, 25, 26-OR goo 1'
+, 35.36-...AND gate, 43...NAN
D gate, 44...inverter, 61...flip-flop data input. 62...Flip-flop positive phase clock input, 62
A...Flip-flop reverse phase clock input. 64...Flip-flop positive side output, 63...
Flip-flop negative output, 20, 30, 40°5
0.60,70...Circuit added to alpha ray resistance, -¥1
Figure 2 Figure 3 Figure ■ 4th page 5 Figure Atsushi 6 Figures 6 and 6r Figure 3 VJ7 Figure T q Figure ηE' Iris Figure 11 'E tz Figure Kuzu! 3 Figure 5E Kaya 14 口￥JtS 国EE vJlg 5 Figure I7 VJzθ Figure

Claims (1)

[Claims] 1. Among the elements constituting the feedback loop, some or all of the elements are provided in pairs, and the inputs of the two elements are connected to each other, and the output signals of the respective elements are connected to each other. A flip-flop circuit that is logically ORed or ANDed. 2. The flip-flop circuit is composed of bipolar transistors, and among the transistors forming the feedback loop, two transistors each having a feedback signal passing through a collector electrode are provided, and the inputs of the two transistors are connected to each other, 2. The flip-flop circuit according to claim 1, wherein the output signal from the collector is logically ORed. 3. The above flip-flop circuit is configured with an emitter-coupled logic circuit, and a feedback signal is obtained from the positive side output, and a signal obtained by logically ORing the positive side output and the inverted signal of the negative side output is used as the feedback signal. 2. The flip-flop circuit according to claim 1, wherein the flip-flop circuit is used.