JPS56147236A - Adding circuit - Google Patents

Adding circuit

Info

Publication number
JPS56147236A
JPS56147236A JP5078780A JP5078780A JPS56147236A JP S56147236 A JPS56147236 A JP S56147236A JP 5078780 A JP5078780 A JP 5078780A JP 5078780 A JP5078780 A JP 5078780A JP S56147236 A JPS56147236 A JP S56147236A
Authority
JP
Japan
Prior art keywords
switches
turned
output
input
becomes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5078780A
Other languages
Japanese (ja)
Other versions
JPS618968B2 (en
Inventor
Norishige Tanaka
Yukihiro Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5078780A priority Critical patent/JPS56147236A/en
Publication of JPS56147236A publication Critical patent/JPS56147236A/en
Publication of JPS618968B2 publication Critical patent/JPS618968B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To simplify the constitution to make the high-speed operation possible, by adding switches and inverters to the first and the third logical gates in the adding circuit which is adapted to incorporation into the sound synthesizing integrated circuit, etc. using the MOS transistor. CONSTITUTION:When input Ai and Bi and 0 together, switches S1 and S4 are turned on, and switches S2 and S3 are turned off, and output Si is the same signal as input Ci, and output Ci+1 becomes 0 due to inversion of NAND gate 1. When inputs Ai and Bi are 1, switches S1 and S4 are turned on, and switches S2 and S3 are turned off, and output Si is the same signal as input Ci, and output Ci+1 becomes 1. When one of inputs Ai and Bi is 1 and the other is 0, switches S1 and S4 are turned off, and switches S2 and S3 are turned off, and output Si becomes the inversion signal of input Ci, and output Ci+1 becomes the same signal as input Ci.
JP5078780A 1980-04-17 1980-04-17 Adding circuit Granted JPS56147236A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5078780A JPS56147236A (en) 1980-04-17 1980-04-17 Adding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5078780A JPS56147236A (en) 1980-04-17 1980-04-17 Adding circuit

Publications (2)

Publication Number Publication Date
JPS56147236A true JPS56147236A (en) 1981-11-16
JPS618968B2 JPS618968B2 (en) 1986-03-19

Family

ID=12868518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5078780A Granted JPS56147236A (en) 1980-04-17 1980-04-17 Adding circuit

Country Status (1)

Country Link
JP (1) JPS56147236A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6275840A (en) * 1985-09-30 1987-04-07 Toshiba Corp Carry selecting adder
WO2011033640A1 (en) * 2009-09-17 2011-03-24 株式会社 東芝 Adder

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5263036A (en) * 1975-10-31 1977-05-25 Nec Corp Full addition and subtraction circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5263036A (en) * 1975-10-31 1977-05-25 Nec Corp Full addition and subtraction circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6275840A (en) * 1985-09-30 1987-04-07 Toshiba Corp Carry selecting adder
JPH0460252B2 (en) * 1985-09-30 1992-09-25 Toshiba Kk
WO2011033640A1 (en) * 2009-09-17 2011-03-24 株式会社 東芝 Adder
US8745120B2 (en) 2009-09-17 2014-06-03 Kabushiki Kaisha Toshiba Adder

Also Published As

Publication number Publication date
JPS618968B2 (en) 1986-03-19

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