SU790340A1 - Exclusive or logic element based on cmds-transistors - Google Patents

Description

one

The invention relates to computing and can be used in the development of universal and specialized computers.

Known logical element exclusive OR, containing eight MOS transistors, forming two parallel branches. In each branch, a pair of p-channel transistors and a pair of n-channel transistors, the gates of which receive the corresponding input signals, are connected in series. the mid points of the two branches are connected to the output of element 1. A disadvantage of the known element is the significant number of components.

An exclusive OR logic element on a KM.1P-transistor is known, which contains an inverter connected between a power bus and a common bus, a bidirectional key, a p-channel transistor and two n-channel transistors, the output of the inverter is connected to a bidirectional switch, and input to the bus of the first input signal, to the gate of the p-channel transistor of the bidirectional switch, to the gate

the first n-channel transistor and to the source of the p-channel transistor, the drain of which is connected to the output bus, to the drains of the two-directional switch transistors and the source of the first n-channel transistor, and the gate of the second n-channel transistor, the drain of which is connected to the source of the first n-channel transistor, and the source to the common bus 21

A disadvantage of the known device 5 is also a significant number of components, which reduces its reliability.

The purpose of the invention is to simplify the device.

20 To achieve a goal, an exclusive OR in a logical element on a CMOS transistor containing an inverter connected between the power line and the common bus,

25 bidirectional key, p-channel and p-channel transistors, while the inverter output is connected to the gate of the n-channel transistor of the two-way switch key, and the input is connected to the bus

30 of the first input signal to the shutter

p-channel transistor bidirectional key and the source of the p-channel transistor, the drain of which is connected to the output bus and to the drains. Bidirectional key transistors, and the gate to the sources of the bi-directional key transistors, to the n-channel gate (Transistor and to the second input signal bus, the drain of the n-channel transistor is connected to the output bus, and the source to the inverter output.

The drawing shows an electrical schematic diagram of the device.

The device contains an inverter 1, formed by a p-channel transistor 2 and a n-channel transistor 3 and connected between the power bus 4 and the common bus 5; the output of inverter 1 is connected to the gate of the n-channel transistor 6 of the bidirectional switch 7 and to the source of the n-channel transistor 8, and the input to the bus of the first input signal A-9, to the gate p of the channel transistor 10 of the bidirectional switch 7 and to the source of the p-channel transistor 11, the drain of which is connected to the output bus 12, on which the OUTPUT signal S is formed, to the drains of transistors b and 10 and to the source of transistor 8, and the gate to the sources of transistors 6 and 10, to the gate of transistor 8 and to the bus of the second input signal B -13.

The device works as follows.

If on bus 9 the first input signal L has a logic O value, then transistors 2.6 and 10 are open and on the output bus 12 a signal is generated corresponding to the value of the second input signal B on bus 13. In this case, if the signal B has a logic O value , the transistor 11 is open, (at its source and drain - the same potential), and the transistor 6 is closed; if signal B has a logical value, then transistor 6 is open (there is the same potential at its drain and source), and transistor 5 is closed.

If on bus 9 the first input signal A is logical, then transistors 2.6 and 10 are closed. At the same time, if on bus 13 the second input signal B has a value

then the transistor

logical

11 is open, and the transistor 8 is closed, and on the output bus 12, the output signal S is logical

if the second input signal is logical

1, then the transistor 11 is closed, and the transistor 8 is open, and on the output bus the signal S has a logic value O ,.

The operation of the device corresponds to the functional table.

B

Reducing the number of transistors and thus the number of connections in the proposed device allows for greater reliability and greater integration.

Oormula invention

Exclusive OR logic element on QVDP transistors containing an inverter connected between

bus power and common bus, bidirectional key, p-channel and p-channel transistors, while the inverter output is connected to the gate of the n-channel transistor. Bidirectional key, and the input-- to the bus of the first input signal, bi-directional key and to the source of the p-channel transistor, the drain of which is connected to the output bus and to the drains of the bi-directional switch transistors, and the gate to the sources of the bi-directional switch transistors, to the gate of the n-channel transistor and to. The second input bus, which is characterized by the fact that, for the sake of simplicity, the drain of the n-channel transistor is connected to the output bus and the source to the output of the inverter.

0

Sources of information taken into account in the examination

1.Valiev KA, Karmazinsky A.M. Digital integrated circuits on TIR transistors. M., Sov. radio,

5 1971, p. 274.

2. US patent 3668425, cl. 3072 .16, 1972.

Claims (1)

Claim Logic element ' ¹ exclusive OR' on KVDP transistors, containing an inverter connected between the power bus and the common bus, a bi-directional key, p-channel and η-channel transistors, while the inverter output is connected to the gate of the η-channel transistor. Bidirectional key , and the input · to the bus of the first input signal, to the gate of the p-channel transistor of the bidirectional key and to the source of the p-channel transistor, the drain of which is connected to the output bus and to the drains of the transistors of the bi-directional key, and the gate to the sources of the transistor bi-directional key to the gate of n-channel transistor and.. the bus of the second input signal, characterized in that, in order to simplify, the drain of the p-channel transistor is connected to the output bus, and the source to the output of the inverter.