SU706880A1 - Storage element for shift register - Google Patents

Description

(54) MEMORY ELEMENT FOR SHIFT REGISTER

1. The invention relates to automation and computing, in particular to the storage elements of digital devices. The known storage cell for the shift register, made on MOSFETs, consists of two stages, each of which contains an inverter and a transfer transistor 1. A low speed and high power consumption are characteristic of such a cell. This is due to the presence of a large parasitic capacitance at the output of each stage, which is a gate – channel capacitance of the inverter key transistor, as well as the presence of through currents in the inverters. A memory cell 2 is also known, which is characterized by its economics in terms of power consumption, since there are no through currents. However, the speed of such a cell is low, since a pause between clock signals is required to ensure normal operation. Closest to the invention of the known technical essence is a memory cell for shift register 3, which contains two memory elements, each of which includes an MOS transistor connected in series and a MIS capacitor connected between the gate and a control transistor drain. The disadvantage of such a cell is its low speed. The reason for this is the need to significantly increase the capacitance of the sources of the control transistors compared to the capacitances of the amplifying transistor fluxes in order to prevent the transmission of the false logical "1 when the logical" O follows the logical "1. An increase in capacities leads to an increase in their charge time, which means a decrease in the speed of the memory cell. The purpose of the invention is to increase the speed by reducing the charge time of the source capacitance of the control MDP transistor. This goal is achieved by the fact that the memory element for the shift register containing the control MOS transistor, the gate of which is connected to the information input of the memory element, is an amplifying MIS transistor, the gate of which is connected to the drain of the control MDP transistor and with the first clock the bus, the drain of the amplifying MDP transistor is connected to the source of the control MOS transistor, the source of the amplifying MDP transistor is connected to the output of the memory element, and the second clock bus is inserted into the discharge MOS transistor, the drain of which is connected to the gate m of the control MOS transistor, the source with the second clock bus, and the gate with the drain of the amplifying MOS transistor.

The drawing shows an electrical circuit of the memory element.

It contains a control MOS transistor 1, an amplifying MOS transistor 2, a discharge MOS transistor 3, clock buses 4 and 5.

It is convenient to explain the principle of operation of the proposed element of the memory, considering the process of shifting information, for which the logical “1 is followed by the logical“ O.

When a logical "1" voltage is applied to the information input, during the action of a high potential of the clock signal on the bus 4, transistors 1 and 2 are opened and the node capacitors are charged at points 6 and 7. Upon reaching the logical voltage at point 8, transistor 3 opens the discharge of the node capacitance of the input to the bus 5, which at that time is under the potential of the tire of zero potential. Transistor 1 is closed, and a logical "1" voltage is stored at the node capacitance at point 8. Upon the completion of the high potential of the clock signal, the bus 4 closes the transistor 2, and at the output of the memory element (first) the logical < 1 > is stored.

Similarly, during the action of a high potential, bus 5 transmits a logical voltage "1" to the same points of the second memory element. The opening transistor of the 9-second memory element discharges the nodal capacitance of point 7 to the busbar 4, which at this time is under the potential of the zero potential bus.

At the same time, the logical input “O. The control transistor of the second memory element of the previous cell (not shown in the drawing) is closed at the same time. Therefore, the node capacity at information input 6 will not be charged. However, with the help of the gate-channel capacitance of the amplifying transistor of the second memory element of the previous cell, during the rise of the high potential of the clock signal on the bus 5, an additional voltage sufficient to unlock the transistor 1 is transferred to the node capacitance of the information input of the first element 8 on the busbar 4. During the decline of the high potential of the clock signal on the busbar 5, this additional voltage is removed with the help of the same capacitance of the gate-channel of the transfer transistor th element of the memory cell pa.m previous minute. As a result, a logical "O" voltage is stored at input 6. Upon the arrival of a high potential of the clock signal on the busbar 4, the transistor 1 is closed and at a zero capacitance point 7 the logical "O" voltage is maintained. Similarly, upon the arrival of a high potential of the clock signal, the transistor 10 is not opened and the logical "O" is also saved at the output of the second element.

Thus, due to the introduction of the discharge transistor into the memory element, the performance is significantly increased compared to the prototype, since there is no need to increase the capacitance of the sources of the control transistor, and therefore the time required to charge this capacitance is reduced.

Claims (3)

1. US Patent No. 3395292, cl. 307-221, pub. 1968. 2. US patent number 3575609, cl. 307-221, pub. 1971. 3. US Patent No. 3808458, cl. 307-221 publ. 1974 (prototype).