SU1599985A1 - Triple-state element - Google Patents

Abstract

The invention relates to electronics, automation, and computing and can be used in digital integrated circuits on MOSFETs. The purpose of the invention is to increase speed. The element contains P-channel MOS transistors 1,2,3 and N-channel MOS transistors 4,5,6. This goal was achieved by introducing new electrical connections between functional elements. 1 il.

Description

The invention relates to electronics, automation, and computing and can be used in digital integrated circuits on MOS transistors.

The purpose of the invention is to increase the speed of the device.

The drawing shows an electrical circuit diagram of an element with three states on MOS transistors.

The element contains P-channel MOS transistors 1-3, N-channel MIS transistors 4-6, bus 7 information signals, bus 8 and 9 control signals and inverse control signals, respectively, output bus 10, power bus 11 and common bus 12.

The sources of the transistors 1 and 2 are connected to the power supply bus 11, the sources of the transistors 4 and 6 are connected to the common bus 12. The drains of the transistors 1 and 4 are connected to the output 1 of another 10, the drains of the transistors 2 and 5 are connected to the gate of transistor 1 bus 8 control signals, the drain of transistors 3 and 6 - with the gate of the transistor 4, and their gates - with the bus 9 inverse control signals. The origins of the transistors 3 and 5 are connected to the bus 7 information signals.

The element works as follows.

In the initial position on the tire 8 i

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 Oh on bus 9

In this case, transistors 2 and 6 are open, which ensures that at the gate of transistor 4 is O, and at the gate of transistor 1 is 1. Transistors 1, 3, 4, and 5 are closed, with the result that the element is in the third state, regardless of the level busbar stress 7.

When 1 arrives at bus 8 and O at bus 9, transistors 2 and 6 are closed, and transistors 3 and 5 open, which ensures the transmission of an information signal from bus 7 to the gates of transistors 1 and 4 and, respectively, the inverse value of this signal on the output bus ten.

Since in the initial position on the gate of the transistor 1, the supply voltage level is set, and on the gate of the transistor 4 - the level

with so with so

00

ate

when transmitting 1 to the terminals of these transistors during the action of the control signal, the P-channel transistor 3 is sufficient, and for the transfer of the O-channel N transistor 5. However, the duration of the control signal must be limited because leakage currents, the potential of the gate of transistor 1 can be shifted by the threshold voltage of transistor 5 or the gate of transistor 4 by the threshold voltage of transistor 3, which leads to the opening of transistor 1 or 4 respectively shit in their chains.

Since the control signals of elements with three states, which are extensively used in controlled buffer devices, MIS BIS devices, most often correspond to this limitation, this drawback of the scheme is not significant.25

Claims (1)

Invention Formula The element with three states, containing the first, second and third P-channel and fourth, fifth and sixth N-channel MIS transistors, the source of the first transistor is connected to the power bus, the sources of the fourth and sixth transistors - with a common bus, the drains of the first and fourth transistors are connected to the output bus, the source of the third transistor is connected to the bus of information signals, the drains of the third and sixth transistors are connected to the gate of the fourth transistor, and their gate is connected to the bus of inverse control signals, characterized in that -optimal, the source of the fifth transistor is connected to the bus data signals, drains of the second and fifth transistors are connected to 3aTjBO- rum first transistor, the gates of the second and fifth transistors are connected to a bus control signals. O-tf