SU725235A1 - Element with three states - Google Patents

Description

(54) ELEMENT WITH THREE STATES

The invention relates to computing and electronics, and may be; used in the creation of integrated circuits on a MOS transistor as an output switch-amplifier for direct integration of OR dke with the output stages. The element can be used in information output devices of static chargers and LSI microprocessors. Elements are known with three states on complementary MOSFETs, containing a push-pull output stage and a symmetric control circuit C. The disadvantage of these elements lies in the considerable power consumption. A known element with three states on complementary MOSFETs, containing a push-pull inverter connected between the power bus and a common bus, p and p-type key transistors connected respectively between the first input of the output push-pull inverter and the common bus and between the power bus And the second input of the output push-pull inverter, the gates of the key transistor, are connected to the information bus, an inverter connected between the power supply bus and the first one, the input of the output push-pull inverter, the input of the inverter The control signal is connected to the control signal bus, and the output to the second input of the push-pull output inverter, and a bi-directional switch connected between the control signal bus and the first input of the output push-pull inverter, the p and n-type bidirectional switch gates are connected respectively to the information bus and the second input of the output push-pull inverter 2. The disadvantage of the known -nta is a significant power consumption and low speed. The purpose of the invention is to reduce power consumption and increase speed. To achieve this goal, an element with three states on complementary MOSFETs, containing an output push-pull inverter connected between the power bus and a common bus, key transistors of n and p-type, connected respectively | between the first input of the output two 725235

Tag inverter and common bus and between the power bus and the second input of the output push-pull inverter, the gates of the key transistors are connected to the data bus, and the first inverter connected between the power bus and the first input of the output push-pull inverter, the input of the first inverter is connected to the direct control signal bus and the output is connected to the second input of the output push-pull inverter, a second inverter is inserted, connected between the output of the first inverter and the common bus, the input of which is connected to the inverse control C bus Nala, and the output - to the first input of the output push-pull inverter ..,.,. ,,

The ria drawing represents an electrical circuit diagram of an element with three states on additional MOSFETs,.

The output push-pull inverter 1 is connected between the power bus 2 and the common bus 3, the p and p-type key transistors 4 and 5 are connected respectively between the first input b of the output inverter 1 and the bus 3 and between the bus 2 and the second input 4 of the output inverter 1, transistors gates 4, 5 are connected to the information bus 8, the first inverter 9 is connected between bus 2 and input b, its output is connected to gateway 7, and the input is connected to the direct control signal bus 10, the second inverter 11 is connected between input 7 and bus 3, output its connected to the input 6, and the input - to the inverse bus, control of the driving signal 12. The output of the inverter 1 is the output of the element 13,

The element works as follows

In the initial state (storage mode for the charger), logical O are received on buses 10 and G2, and a logical H is set at the output of the first inverter 9, and a result of which, regardless of the signal value bus 8, both transistors of the output push-pull inverter 1 are closed and a third state is established at its output.

In the information transfer mode (read mode for memory), the buses 10 and 12 receive logical and O, respectively, the p-channel transistor of the first inverter 9, and the p-channel transistor of the second inverter 11 open, closing the first and second inputs of the push-pull inverter 1. On arrival logical Oh on the information bus 8 is open, the key transistor 5 is p-type, and the second key transistor 4-type is closed. As a result, at the closed inputs of the output push-pull inverter 1, the logical

 1, and the information transmitted at its output is logical O. When the logical H arrives on the bus 8, the key transistor 4 is open, and the key transistor 5 is closed, the logical O is set at the closed inputs of inverter 1, and the information is transmitted at its output.

Thus, the element provides the appearance of an information signal at its output when a logical signal arrives on the direct control signal bus and a logical signal O on the inverse control signal bus. At opposite values of logical signals on the indicated tires, the element is in the third state.

The transmission time of the logical -O and H is approximately the same, the speed increases approximately 1.5 times compared with the known

scheme.

A reduction in power consumption is ensured by the fact that an n-type inverter 9 is connected between the inputs of inverter 1 and a p-type inverter 11 transistor is connected in parallel, so the logic voltage is fed to input 7 directly, and to input 6 through the p-type inverter transistor 11, and the logic voltage O is fed to input 6 directly, and to input 7 through an n-type transistor of inverter 9. As a result, the corresponding transistor of the output push-pull inverter 1 is more quickly closed, which reduces the value of the through current and the time of its flow, and this leads to a decrease in power consumption.

Claims (2)

1. The USSR USSR Certificate in Application No. 2583020 / 18-21, 24.02.78. 2. US Patent 4037114, cl. 307-205, 1977.