SU1566410A1 - Reading device for programmed logic matrix - Google Patents

Abstract

This invention relates to microelectronics and is intended for use in programmable logic integrated circuits manufactured using CMOS technology. The aim of the invention is to expand the functionality of the device by turning off the power supply voltage in the programming mode. The device includes a power supply driver, a trigger reset circuit, and a key transistor. The input of the power voltage driver is the input for setting the operating mode of the device, the drain of the key transistor is the information input of the device. The trigger reset circuit consists of two key transistors, the gates of which are combined and connected to the input of the power supply shaper, and the drains are connected respectively to the input and output of the trigger. 1 il.

Description

This invention relates to microelectronics and is intended for use in programmable logic integrated circuits manufactured using MOS technology.

The purpose of the invention is to expand the functionality of the reader.

The drawing shows the electrical circuit of the device.

The diagram shows power supply driver 1, device mode setting input 2, power driver voltage output 3, unbalanced trigger 4, input 5 and output 6 of an unbalanced trigger, output inverter 7. first key transistor 8 and second key transistor 9 of circuit 10 resetting the asymmetrical trigger, the load transistor 11 and the switching transistor 12 of the power supply voltage driver, the bus 13 of the power supply voltage and the bus 14 of the zero potential of the device, the load transistor 15, the first switching transistor hist 16. The second pull-up transistor 17 and the second switching transistor 18 is asymmetrical trigger, load transistor 19 and the switching transistor 20 of the inverter output, information output apparatus 21 and vhod22, a key transistor 23 device, the memory cell 24 a programmable logic array.

Trigger 4 is an asynchronous trigger in CMOS - performance on transistors 15 - 18. Transistors 15 and 17 are p-channel, transistors 16 and 18 are n-channel. The origins of p-channel transistors are connected to output 3 of power generation unit 1, for example, the power supply of the trigger, the sources of the n-channel transistors are connected to the common bus 14. The gates of the transistors 15 and

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16 are combined with the drains of transistors 17 and 18 to form a reverse trigger connection. The gates of transistors 17 and 18 are connected to the drain of transistors 15 and 16. to form a second reverse trigger connection. Wherein

L / | (ll | lllllll

 VT17 L / VT15 L vT18 L / VT16

where W is the channel width of the corresponding transistor t;

L is the channel length of the corresponding transistor.

Inverter 7 is a CMOS inverter consisting of a p-channel transistor 19 and an n-channel transistor 20. The source of transistor 19 is connected to the output 3 of power supply unit 1 of the trigger voltage. The source of the transistor 20 is connected to the common bus 14. The gates of the transistors 19 and 20 are combined and connected to the output 6 of the trigger 4. The drains of the transistors 19 and 20 are connected and represent the output 21 of the reader of the architectural bit of the programmable logic array. Transistors 8 and 9 zero the input and output of trigger 4. The gates of these transistors are combined and connected to the input of the power supply shaper.

-The device works as follows.

Depending on the level of the signal at input 2, the reader is in two modes. If the signal is at a logic zero level, the read mode is set. In this mode, transistors 8 and 9 are closed (trigger blocking is removed) and the supply voltage of trigger 4 at output 3 opens transistor 23. If memory cell 24 is in a non-conducting state, input level 5 of trigger 4 sets the level of the logical unit, and output 6 level logical zero. This level is inverted from the input 6 by the inverter 7 and the level of the logical unit is set at the output 21 of the device.

If the memory cell 24 is in the conducting state, then the input level 5 of the trigger 4 sets the level of logical zero, and the output 6 - the level of the logical unit. At reader output 21, a logical zero level is set.

If the signal arriving at input 2 is equal to the level of a logical unit, the programming mode is set. In this mode, the supply voltage at output 3 is zero, transistors 8 and 9 open, and the potential at input 5 and output 6 of the flip-flop is zero.

The signal at output 3, equal to the logic zero level, closes the transistor 23, and the high voltage required to program the memory cell 24 and the input to the input 22 is not transmitted to the device circuits 4 and 7.

In the read mode, the reader device is set to one of two states, and the circuit does not consume the current of the power source. This state can be changed during the transition to the programming mode, when the signal levels on both

the shoulders of the trigger 4 are zero, i.e. trigger 4 is reset and ready, when entering read mode, to re-read information from input 22.

The proposed device can operate in read and program modes, and in program mode, the reader device is zeroed and ready to read information from the reprogrammed architectural bit.

Claims (1)

Invention Formula A reader for a programmable logic array containing an unbalanced trigger, the output inverter of which is connected to the output of an unbalanced trigger, and the output is an information output of the device, which is different in that. in order to expand the functionality of the device by turning off the power supply in the programming mode, it contains a power supply driver consisting of a CMOS inverter, input setting the operation mode of which is the input of setting the operation mode of the device, the key transistor whose drain is the information input of the device and the gate and source are connected respectively to the output of the power supply shaper and the input of the unbalanced trigger, the zeroing circuit of the single-ended trigger consisting of first and second key transistors, the sources of which are connected and connected to the zero potential bus of the device, the gaps are combined and connected to the input of the power supply voltage generator, the drains of the first and second key transistors connected to the input and output of an unbalanced trigger, respectively; the supply voltage buses of the unbalanced trigger and the output inverter are combined and connected to the output of the voltage driver,