SU1480116A1 - Mds-transistor-built logic element - Google Patents

Abstract

The invention relates to computing and can be used in MTD integrated circuits as a multifunctional logic element. The aim of the invention is to simplify the element by reducing the number of MTD transistors. The element contains six MTD transistors 1-6 of the first type and five MOS transistors 7-11 of the second type. The input signals of two variables are fed to the input buses 16 and 17, and the output signals are removed from the output buses 12-15, on which, respectively, the functions of negative conjunction and disjunction, comparison, and inversion are implemented. Simplification of the element is achieved due to the multifunctional use of MOSFETs taking into account their property of two-sided conductivity. 1 il.

Description

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The invention relates to computing and can be used in MIS integrated circuits as a multifunctional logic element.

The aim of the invention is to simplify the device by reducing the number of VDP transistors by applying both potential gate links between transistors and current, multifunctional use of MOS transistors taking into account their bi-directional conductivity properties, thereby reducing the number of transistors arriving to perform a single logical function.

The drawing is a schematic diagram of a logic element on MOS transistors with an induced channel.

The logic element on MOSFETs contains six transistors 1-6 of the first type and five transistors 7-11 of the second type.

The path of the second transistor 2 of the first type, the drains of the third 9 and fourth 10 and the source of the first 11 transistors of the second type are connected to the first output bus 12. The source of the second transistor 8 of the second type, the drains of the third 3, fourth 4 and gate of the fifth 5 transistors of the first type, as well as the gate n of the second transistor 11 of the second type are connected to the second output bus 13.

The drains of the fifth and sixth six transistors of the first type and the drain of the second transistor 11 of the second type are connected to the third output bus 14.

The drains of the first 1 and second 3, the source of the sixth 6 transistors of the first type and the drains of the first 7 and second 8 transistors of the second type are connected to the fourth output bus 15.

The gates of the first 1, 7 and third 3, 9 transistors of both types are connected to the first input bus 16, and the gates of the second 2, 8 and fourth 4, 10 transistors of both types and the gate of the sixth transistor 6 of the first type are connected to the second input bus 17. Origins not the first 1, third 3, fourth 4, and fifth five transistors of the first type are connected to the power bus 18, and the sources of the first 7, third 9, and fourth 10 transistors of the second type are connected to a common bus 19.

The logical element operates as follows.

Logic signals XI and X2 are supplied to the input buses 16 and 17. On the first output bus 12, the conjunction function of the auxiliary input logic signals Y1 XI X2 is implemented. On the second output bus 13, the disjunction function of the same signals Y2 XI + + X2 is implemented. On the third output bus 14, the comparison function Y3 XI X2 + XI X2 is implemented, and on the fourth output bus 15, the negation function Y4 XI.

When applied to the input bus sets of 0.0 first 1, second 2, third 3, fourth 4 and sixth 6 transistors of the first type are open, and the first 7, second 8, third 9 and fourth 10 transistors of the second type are closed. In this case, a signal 1 is set on all output buses 12-15.

When applied to the input buses of the set 1.1, all of the above transistors change their state of conduction to the opposite and on the first

12, the second 13 and the fourth 15 output lines are set by the signal O and on the third output line 14 by means of an open fifth transistor 5 of the first type — signal 1.

When a set of 0.1 is applied, the first-1 and third 3 transistors of the first type and the second 8, the fourth 10 and fifth 11 transistors of the second type are opened. At the same time, on the first 12 and third 14 output buses, the signal O is set, and on the second 13 and fourth 15 output tires - the signal 1.

When fed to the input tires 1G and 17 logical set 1.0 on all output tires, except the second bus

13, the signals O are set. Thus, the proposed

The device contains 11 KDP transistors and performs four logic functions, i.e. has a better performance than the prototype device, which increases the reliability and manufacturability of the device.

Connecting to the third output bus 14 of the inverter, for example, made on additional type of MOSFETs, additionally allows to implement another comparison function Y5 X1 X2 + XI X2, which expands the functionality of the logic element while maintaining the advantage over the prototype device in complexity.

Claims (1)

Invention Formula A logic element on MIS transistors containing six transistors of the first type and five transistors of the second type, sources of the first, third and fifth transistors of the first type are connected to the power bus, and the sources of the first and third transistors of the second type the bus, the first and third transistor gates of the first type and the third transistor of the second type are connected to the first input bus, and the second and fourth transistors of both types are connected to the second input bus, the second and second transistors are connected to the second transistor. types are connected respectively with the first and second output buses, the drains of the first and second, as well as the third and fourth transistors of the second type are combined in pairs, the drains of the third and fourth and the gate of the first transistor of the first type are connected to the gate of the second transistor of the second type, the drain of which is connected to the drain of the fifth and sixth transistors of the first type and is connected to the third output bus, the drain of the first and second transistors of the first type are connected to the fourth output bus, characterized in that, in order to simplify the devices The gates of the first transistor of the second type, the drain of which is connected to the fourth output bus, are connected to the first input bus, the source of the second hinge type and the drain of the fourth transistor of the second type are connected to the first output bus, the gate and the source of the sixth transistor of the first type are connected respectively to the second input and fourth output buses, the drain of the third transistor of the first type is connected to the second output bus, and the sources of the fourth transistor of the first and second types are connected. respectively to the power rail and to the common tire.