SU1562967A1 - Logic element with states on complementary mds-transisistors - Google Patents

Abstract

The invention relates to computing and electronics and can be used to create large integrated circuits (LSIs) as an output amplifier for an external capacitive load. The aim of the invention is to increase the speed of an element with three states. The element contains an information bus, a power bus 11, an output bus 12, a common bus 13, a first 14 and a second 15 control bus. To achieve the objective, a forcing capacitor 16 and an additional P-type transistor 6 are introduced into the element. This allows preloading of the output bus 12 and accelerating the working phase of the cycle — discharge of the output bus 12 through the transistor 10 of the output amplifier 17. 1 sludge.

Description

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amplifier 17. The first inverter, containing 45 6 p-type. In this case, the transistor 9 is a p-tactile transistor 7 and 8, connected between the supply bus 11 and the gate of the transistor 10, the input of the first inverter is connected to the first bus 14 of the control signal, and its output is connected to the gate of the transistor 9 17, the output of which is connected to the output bus 12.

The logical element works as follows.

In the initial state, a log enters the control slit 14. Oh, on control bus 15 - Log. 1. Tran55

The pa is closed, the 10 p-type transistor is open, and a log is fed to the output bus 12. О due to the discharge through the transistor 10 n-type. If 1 the signal is given Log. 1, then on the gates of the transistors 9 and 10 of the p-type and n-type, the signal Log is set. Oh, coming through the open transistors 3, 4, 6 and 8 p- and n-type. In this case, the p-type transistor 9 is open, and the n-type transistor 10 is closed. The output voltage is charged through a p-type transistor 9 and a Log signal is installed on it. one.

6 p-type. In this case, the transistor 9 p-ti

The pa is closed, the 10 p-type transistor is open, and a log is fed to the output bus 12. О due to the discharge through the transistor 10 n-type. If 1 the signal is given Log. 1, then on the gates of the transistors 9 and 10 of the p-type and n-type, the signal Log is set. Oh, coming through the open transistors 3, 4, 6 and 8 p- and n-type. In this case, the p-type transistor 9 is open, and the n-type transistor 10 is closed. The output voltage is charged through a p-type transistor 9 and a Log signal is installed on it. one.

Claims (1)

Invention Formula A logic element with three states on complementary MOS transistors, containing two p- and n-type key transistors, the first and second inverters, the push-pull output amplifier, the information signal bus, the first and second control signal busses, the power bus, the output and the common bus, the information signal bus is connected to the gates of the p-type and n-type key-1 transistors, the n-type drain of the key transistor is connected to the second input of the output amplifier connected between the power line and the common bus, the output of which connected to the output the same bus element, the first inverter is connected between the power bus and the second input of the output amplifier, the input 0 the first inverter is connected to the first control signal bus, and its output is connected to the first input of the output amplifier, the second inverter is connected between the p-type drain of the key transistor and the common bus, the input of the second inverter is connected to the second control signal bus, the input of the output amplifier, characterized in that, in order to increase the speed of the element, an additional p-type MOS transistor is inserted in it, connected between the p-type drain of the key transistor and the first input of the output amplifier, otorrhea connected to the second bus control signal and a booster capacitor which is connected between the drain of the p-type transistor and the common bus.