SU1734206A1 - Mos-transistor-based gate - Google Patents

Abstract

Purpose: use in MDP-integrated circuits as a multifunctional logic element. The essence of the invention: the device contains five transistors of the first type and four transistors of the second type, four output buses and two input buses. 1 il.

Description

The invention relates to computing and can be used in MIS integrated circuits as a multifunctional logic element.

Known logic element on MOS transistors, containing seven transistors of the first type and seven transistors of the second type.

The disadvantage of such a device is a significant number of transistors.

The closest in technical essence to the device claimed is a logic element selected as a prototype on CMPE transistors, containing six transistors of the first type and five transistors of the second type.

A disadvantage of the known device is the significant number of transistors, reducing the number of which in integrated performance will reduce the area of the device and, consequently, increase the percentage of the yield of ICs, and in the discrete version increase reliability.

The purpose of the invention is to increase the percentage of yield of IP in the case of an integrated design and increase reliability in the case of discrete execution of a logic element on MOS transistors.

This goal is achieved in that a logical element on MOS transistors containing five transistors of the first type and four transistors of the second type, sources of the first, third transistors of the first type are connected to the power bus, and sources of the first, third, fourth transistors of the second type are connected to the first the input bus, the gate of the first p transistor of the first type and the gates of the second, fourth, transistors of the second type are connected to the second input bus, the drain of the second transistor of the first type, the drains of the third, fourth transistors the second type is connected to the first output bus, the drains of the third and fourth transistors of the first type are connected to the second output bus, the drain of the fifth transistor of the first type is connected to the third output bus, the drains of the first transistor of the first type and the first transistor of the second type are connected the source of the first transistor of the first type connected to the first input bus, the source of the second transistor of the first type.

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connected to the second output bus, the source of the fourth, the gate of the second transistor of the first type and the drain of the second transistor of the second type connected to the third output bus, the gate of the fourth transistor of the first type and the source of the second transistor of the second type connected to the fourth output bus

The drawing shows a schematic diagram of a logic element on MTD transistors.

The logic element on the MTD transistors contains the first output bus 1, to which the drain of the second transistor 2 of the first type, the drains of the third 3 and fourth 4 transistors of the second type, the second output bus 5, to which the drains of the fourth 6 and third 7 are connected, the source of the second 2 transistors of the first type, the third output bus 8, to which the drain of the fifth 9 is connected, the source of the fourth 6, the gate of the second 2 transistors of the first type, the drain of the second 10 of the transistor of the second type, the fourth output bus 11, to which the drain of the first 13 is connected, the source of watts The first 10 transistors of the second type, the first input bus 14, to which the gates of the third 7, first 12, the source of the first 9 transistors of the first type, the gates of the first 13, third 3 transistors of the second type, the second input bus 15, to which the gates are connected, are connected An additional 9 transistor of the first type, the gate of the second 10, fourth 4 transistors of the second type, power supply bus 16, to which the sources of the first 12, third 7 transistors of the first type are connected, a common bus 17, to which the sources of the first 13, third 3, fourth 4 are connected transistors of the second type but.

The device works as follows.

Logic signals are provided to the input buses 14 and 15. On the first output bus 1, the conjunction function of the complementary input logic signals Y1 X1 X2 is implemented. On the second output bus 5, the function of disjunction of the same signals Y2 X1 + X2 is implemented. On the third output bus 8, the comparison function Y3 X1X2 + X1X2 is implemented, and on the fourth output bus 11 - the negation function Y4 X1.

When applied to the input bus sets of 0.0, respectively, the first 12, second 2, third 7, fifth 9 transistors of the first type are open, and the fourth 6 are of the first type, the first 13, second 10, third 3, and the fourth are four transistors of the second type. At the same time on the first 1, second 5, and fourth

11 output buses set signal 1, and on the third 8 output bus - O.

When fed to the input bus sets 1, 15, respectively, the first 12, second 2, third 7, fifth 9 transistors of the first type are closed, and the fourth 6 transistor of the first type and the first 13, second 10, third 3, fourth 4 transistors of the second type are open . At the same time, on all output buses 1, 5, 8, 11, the signal O is set.

When applied to the input bus sets of 1.0, respectively, the first 12, second 2, third 7 transistors of the first type and the second 10, fourth transistors of the second type are closed, and the fourth 6, fifth 9 transistors of the first type and the first 13, third third transistors of the second type open. In this case, the signal O is set on the first 1 and fourth 11 output buses, and the signal 1 sets on the second 5 and third 8 output tires.

When applied to the input bus sets of 0.1, respectively, the first 12, third 7 transistors of the first type and the second 10, fourth 4 transistors of the second type are open, and the second 2, fourth 6, fifth 9 transistors of the first type and the first 13, third 3 transistors the second type is closed. In this case, the signal O is set on the first 1 output bus, and the signal 1 is set on the second 5, third 8 and fourth 11 output buses.

Reducing the number of transistors will reduce the area of the device in the integrated design, which in turn will increase the percentage of yield of IP, and in discrete design will increase the reliability of the device.

Claims (1)

The invention of the logic element on MOS transistors, containing five transistors of the first type and four transistors of the second type, the sources of the first and third transistors of the first type are connected to the power bus, and the sources of the first, third and fourth transistors of the second type are connected to a common bus, the gates of the first and third transistors of the first type and the first and third transistors of the second type are connected to the first input bus, the gate of the fifth transistor of the first type and the gates of the second and fourth transistors of the second type connected to the second input bus, drain of the second transistor of the first type, drains of the third and fourth transistors of the second type are connected to the first output bus, drains of the third and fourth transistors of the first type are connected to the second output bus, drain of the p transistor of the first The type is connected to the third output bus, the drains of the first transistor of the first type and the first transistor of the second type are connected to the fourth output bus, characterized in that, in order to increase the percent yield of usable integrated circuits in the case of integrated performance and increase reliability in the case of discrete execution of the logic element MOSFET transistors the first type of the transistor is connected to the first input bus, the second transistor of the first type is connected to the second output bus, the fourth source, the second transistor of the first type and the second transistor of the second type are connected to the third output bus, the fourth transistor of the first type and the second transistor Type connected to the fourth output bus.