SU1064470A1 - Polyfunctional logic element based on insulated-gate field-effect transistors - Google Patents

Abstract

MULTIFUNCTIONAL LOGICAL ELEMENT ON MDP-TRANSISTORS, containing the first, second and third information transistors of n-type, connected in series, fourth, fifth and sixth information transistors of the n-type, connected sequentially, four, four input buses, direct and inverse buses control signal, i.e., in order to increase reliability, the first, second and third information transistors are connected between the output and common buses, the fourth, fifth and sixth information transistors are included between Khodnev and general tires, the first, second and third load transistors are p-type are connected in series between the power supply bus and an output bus, the fourth, fifth and sixth nagruzrchnyo; p-type transistors are connected in series between the power supply bus and the output bus, the drain of the first p-type blocking transistor is connected to the power supply bus, and the source is connected to the drain of the third p-type load transistor, the drain of the first p-type switching transistor is connected to the second is a p-type ruler transistor, and the source is connected to the sixth p-type load transistor, the second p-type switching transistor is connected to the pin of the fifth p-type load transistor, and the source connected to the output bus, the drain of the second n-type blocking transistor, is connected to the common bus, and the source is connected to the drain of the first n-type information transistor, the drain of the third n-type switching transistor is connected to the drain of the second n-type information transistor, and the source to the drain of the fourth n-type information transistor, the drain of the fourth switching transistor .n-type is connected to the drain of the p-type fifth load transistor, and the source is connected to the output bus, the drain of the second n-type blocking transistor. connected to a common bus, and the source is connected to the drain of the first n-type information transistor, the drain of the third n-type switching transistor is connected to the drain of the second information transistor, n-type, and the source is connected to the drain of the fourth n-type information transistor the n-type switching transistor is connected to the drain of the n-type information transistor, and the source is connected to the output pin, the gates 4i of the first load transistor vl of the p-type and the third information transistor of the p-type are connected to the first by the input bus, the gates of the second p-type load transistor and the second information transistor of the p-type are connected to the second input bus, the gates of the fifth p-type load transistor and the fifth information transistor of the rm type are connected to the third input bus, the gates of the sixth p-type load transistor and the fourth n-type information transistor are connected to the fourth input bus, the gates of the first and sixth n-type information transistors and the third and fourth

Description

In addition, p-type load transistors are connected to a direct control signal bus, commuting gates

and the blocking transistors are connected to the inverse control signal bus.

one

The invention relates to computing and can be used in the development of universal and specialized digital computers.

A multifunctional logic element is known, containing two elements of equivalence and element AND element, NOT, each element of equivalence having one informational and one controlling input-, the inputs of elements of equivalence are connected to the inputs of the element I, the output of which is connected to the direct output of the logical element and with the input element NOT, the output of which is connected with the inverse output of the logic element Cl 3.

A disadvantage of the known device is the low reliability of the circuit due to the large number of hardware, which is determined by the redundant functionality of this device.

Closest to the proposed is a multifunctional logic element on MOS transistors, containing the first, second and third information transistors of n-type, connected in series, the fourth, fifth, and sixth information transistors of n-type, connected in series with four input buses.

direct and inverse control signal 2.

The disadvantage of this element is low reliability due to the large number of circuit components.

The purpose of the invention is to increase reliability.

The goal is achieved by the fact that in a multifunctional logic element on MLC transistors containing first, second and third information transistors of n-type, connected in series, fourth, fifth and sixth information transistors of n-type, connected in series, four input buses, direct and inverse busbars; control, first, I second and third information transistors are connected between the output and common buses, fourth, fifth and sixth information transistors are connected between the output and common buses, the first second and third p-type load transistors are connected in series between the p-tus source bus and the output bus, the fourth, fifth, and sixth p-type load transistors are connected in series between the power supply bus and the output bus; the drain of the first p-type blocking transistor is connected to

0 bus power source and source

the p-type third load transistor is connected to the drain, the p-type first switching transistor is connected to the p-type second loading transistor, and the source is connected to the p-type sixth load transistor, the p-type second switching transistor is connected to the drain the p-type load transistor, and the source is connected to the output bus, the drain of the second n-type blocking transistor is connected to the common bus, and the source is connected to the cTOf of the first n-type information transistor, the drain of the third switch The n-type transistor is connected to. the drain of the second information transistor p-type, and the source to the drain of the fourth information transistor of n-type, the drain of the fourth

The g-type switching transistor 0 is connected to the drain of the p-type load transistor, and the source is connected to the external bus, the drain of the second blocking transistor of the n-type

5 is connected to a common bus, and the source is connected to the drain of the first n-type information transistor, the third drain on the switching L-type transistor is connected to the drain of the second

0 of the information transistor is n-type, and the source is to the CTORy of the fourth information transistor of n-type, the drain of the fourth switching transistor of n-type is connected to the drain of the fifth information transistor of n-type / and the source is connected to the output bus, the gates of the first load transistor p- type and third n-type information transistor are connected to the first input bus, the gates of the second p-type load transistor and the second information transistor of n-type are connected to the second input bus, the gates of the fifth load transistor p-type stoppers and p-type information transistor are connected to the third input device, the gates of the sixth p-type load transistor and the fourth n-type information transistor are connected to the fourth input bus of the first and sixth n-type information transistors and the third and fourth p-type load transistors are connected to the control bus of the direct control unit., switching gates and blocking transistors are connected to the control inversion signal bus. On the “ftezhe”, a schematic of the proposed multifunctional logic element “and MOSFET transistors” is presented. Transistors 1-3 p-type are connected in series with each other. Transistors of 4-6p-type are connected sequentially between themselves, transistors 7-9 of p-type are connected in series between each other, transistors 10-12 p-type connected in series between, side the 13p-type transistor is connected to the drain of transistor 9, the p-type aistobo 14 drain is connected to the drain of transistor 8, and the source is connected to the drain of the IS transistor, the P-type toanzistooa 15 is connected to the drain, the transistor 11, the 16 m-type transistor connected to the drain of the transistor 1, the drain of the transistor. D7p-type connected to the drain of the transistor 2, and the source - to, the drain of the transistor 4, the drain of the transistor 18p -type connected to the drain transis

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P

2f of the torus 5, the drain of the transistors 3, b and 16 are connected to common and; not 19, the origins of transistors 1, 4, 9, 12, 15 and 18 are connected to the output bus 20, the drain of transistors 7, 10 and 13 are connected to the source bus 21 power, the gates of the transistors 3 and 7 are connected to the first input bus 22, the gates of transistors 2 and 8 to the second input line 23, the gates of transistors 5 and 11 to the third input line 24, the gates of transistors 4 and 12 to the fourth input line 25, the gate of the transistors 1, 6, 9 and 10 are connected to the bus 26 of the direct control signal, the gates of the transistors 13-18 are connected to the bus 27 of the inverse c controlling drove. The device works as follows. An inverse signal is applied to the bus 27 with respect to the signal on the bus 26, therefore, the g-groups of the Transistors 1, 6, 13, 14, 15 and 9, 10, 16, 17, 18 operate in phase mode. If the Uverv group of transistors is on (the signal on bus 26 is 17;), then the multifunctional element performs the logical function I2-OR-HE2, if the second group of transistors is turned on, then the logical function OR2-1K-HE2 is performed. The technical and economic effect of using the proposed device is to increase the reliability due to an increase in the yield of products, as the number of transistors in the device decreases. . Elit I

Claims (1)

MULTIFUNCTIONAL LOGIC ELEMENT ON MOSFET TRANSISTORS, containing the first, second and third information transistors of η-type, connected in series, fourth, fifth and sixth information transistors of and-type, connected in series, four input buses, bus direct and inverse control signal , resulting in the fact that, in order to increase reliability, the first, second and third information transistors are connected between the output and common buses> the fourth, fifth and sixth information transistors are connected between the output and common buses, the first, second and third p-type load transistors are connected in series between the power supply bus and the output bus, the fourth, fifth and sixth p-type load transistors are connected in series between the power supply bus and the output bus, drain of the first blocking transistor ρ- of the type is connected to the power supply bus, and the source is connected to the drain of the third p-type transistor, the drain of the first p-type switching transistor is connected to the drain of the second p-type load transistor. is the same as the drain of the sixth p-type load transistor, the drain of the second ρ-type switching transistor is connected to the drain of the fifth ρ-type load transistor, and the source is connected to the output bus, the drain of the second p-type blocking transistor is connected to the common bus, and the source is connected to the drain of the first η-type information transistor, the drain of the third η-type switching transistor is connected to the drain of the second η-type information transistor, and the source is to the drain of the fourth η-type information transistor, the drain of the fourth switching o the i-type transistor is connected to the drain of the fifth p-type load transistor, and the source is connected to the output bus, the drain of the second η-type blocking transistor is connected to the common bus, and the source is connected to the drain of the first i-type information transistor, the drain of the third switching transistor η-type is connected to the drain of the second information transistor, η-type, and the source to the drain of the fourth information transistor n-type .g pa, the drain of the fourth switching transistor and-type is connected to the drain of the fifth information transistor η-type, the source is connected to the output bus, the gates of the first p-type load transistor and the third η-type information transistor are connected to the first input bus, the gates of the second p-type load transistor and the second information transistor, η-type are connected to the second input bus, the fifth load gates the ρ-type transistor and the fifth rr-type information transistor are connected to the third input bus, the gates of the sixth p-type load transistor and the fourth η-type information transistor are connected to the fourth input discharge bus gates of the first and sixth information ican tran * · η-type and third and chetver1064470 load transistors of p-type are connected to a direct control signal bus, and switching valves blocking transistor connected to a bus inverted control signal.