SU1064471A1 - Polyfunctional logic element based on insulated-gate field-effect transistors - Google Patents

Abstract

MULTIFUNCTIONAL LOGICAL ELEMENT ON MDP-TRANSISTORS, containing the first, second informational and first switching transistors n-THiia, connected in series, the first, second load transistors of the p-type, connected in series, two information buses, direct and inverse buses of control signals, drain .the first h-type information transistor is connected to the common bus, the drain of the first p-type load transistor is connected to the power supply bus, the gates of the first information n-type and the first load the p-type transistors are connected to the first information bus, the gates of the second information n-type and the second load p-type transistors are connected to the second information BUS, and the aft of the first switching transistor of the n-type is connected to the direct control signal bus, depending on t & l, that, in order to improve reliability, a second p-type switching transistor is inserted in it, which is connected in series with the first and second p-type load transistors, the first p-type and the second n-type blocking transistors, the third p-type and fourth h-type switching transistors, the drain of the first blocking transistor of p-type is connected to the power supply bus, sources of the first, fourth p-type and second, third p-type switching transistors are connected to the output bus, the common bus is connected the drain of the second n-type blocking transistor, the source of the p-type first blocking transistor, is connected to the drain of the second p-type switching transistor, (L, the drain of the third p-type switching transistor is connected to the drain of the second load transistor p-type oracle, the fourth n-type switching transistor drain is connected to drain 2 of the second n-type information transistor, the source of the second n-type blocking transistor is connected to the drain of the first, switching transistor O) n-type, the gate of the second switching 0 transistor p- The type is connected to the direct control bus, the gates of the first p-type, the second l-type blocking third p-type, the fourth n-type xc switching transistors are connected to the inverse control signal bus.

Description

The invention relates to computing and can be used in the development of universal and specialized digital computing matin.

A multifunctional pogic element is known that contains two elements of equivalence and an element AND, the element is NOT / and each element of equivalence has one information and one control input, the outputs of the elements are equivalent to the network connected to the inputs of the element AND whose output is connected to the forward output of the logic element and to the input an NOT element whose output is associated with the inverse output of a logic element tl

A disadvantage of the known device is the low reliability of the circuit due to the large amount of hardware, which is determined by the redundant functionality of this device.

The closest to the proposed is a multifunctional logi

, a cic element containing two information buses, direct and inverse bus control signals, the first, the second information, and the first; switching transistors pa that are connected in series, the first, the second p-type load transistors, connected in series, a two-input logic element K-NOT, two two-input logic elements OR-NOT, a traction of logical elements NOT, a drain of the first information transistor. The type is connected to a common bus, the drain of the first p-type load transistor SO | E (Dinen with the power supply bus, the gates of the first n-type information and the first load p-type of the transistors are connected to the peo information bus, gates cerned n-type information and second n.agruzochnogo p-type transistors are connected to the second infoomatsionnoy bus gate of the first switching transistor T1 type connected to the bus forward control signal 2. The disadvantage of the element is low reliability due to the large number of circuit components.

The purpose of the invention is to increase the reliability of the multifunctional logic element.

To achieve this goal, a multifunctional logic element of NMPD transistors, containing the first, second informational and first switching transistors; , connected in series, first, second p-type load transistors, connected in series, two information buses, direct and inverse control signals, the drain of the first n-type information transistor is connected to a common bus, the drain of the first load transistor, p-type is connected to a bus power supply, the gates of the first informational n-type and the first load p-type transistors are connected to the first information bus gates of the second .informational n-type and second load p-type transistors connected to the second information bus, the gate of the first switching transistor of n-type is connected to the bus of the direct control signal; a second switching p-type toanzisto switch is introduced: which is connected in series with the first p-type load transistors, the first p-type and second p-type blocking transistors, third p-type and fourth p-type switching transistors, the drain of the first p-type blocking transistor is connected to the power supply bus, - the first, fourth p-type and second, third p-type sources are connected to the output bus one hundred second second blocking transistor of a p-type, the source of the first blocking p-type transistor is connected to the drain of the second switching transistor, the third commutator of the p-type transistor is connected to the second o load tra: p-type nsistor, drain of fourth commuting i-type transistor is connected to the drain of the second ti-type information transistor, source of the second n-type blocking transistor is connected to the drain of the first r-type switching transistor, gate of the second p-type transistor connected to the Vshnaya direct control signal, the gates of the first, second n-type blocking and third p-type, fourth tf-type% of commutator transistors are connected to the chain-mounted transistor. inversion control signal. " On. Drawing P is a schematic diagram of the proposed multifunctional logic element on MOS transistors. .

The first 1, second 2 informational and first KOMuiytiruyushchy 3 P-type transistors are included. In series, the first 4, second 5 load and second switching transistor b: p-type ora are connected in series, the source of the first blocking transistor

7p-type is connected to the drain of the transistor b, the source of the second-arc blocking

The h-type transistor 8 is connected to the drain of the transistor 3 / the drain of the third switching transistor / p. E type is connected to the drain of transistor 5, the drain of the fourth switching transistor of n-type 10 is connected to the drain of transistor 2. The drain of transistors 4 and 7 are connected to bus 11 power source. The sources of the transistors 3, 10 Ib, 9 are connected to the output bus 12 The drains of the transistors 1 and 8 are connected to the common bus 13. The gates of the transistors G and 4 are connected to the first information bus 14, the gates of the transistors. 2 and 5 - with the second information bus 15, the gates of the transistors 3 and 6 - with the bus 16 of the forward control signal, the gates of the transistors 7-10 with the BUS 17 inverse control signal. The device works as follows. If there are levels of logical units and logic zero on buses 16 and 17, the first switching 3, the third switching and 9, and the first blocking 7 transistors and the second and fourth fourth switching and the second 8 blocking transistors are open. In this case, a combination of logical signals 00, 01% Yu n. A first 14 and second 15 iformatsionnyh buses provide the formation of a logical unit on the bus 12 through the open load transistors 4 and 5, respectively. The combination of 11, input logic sigals provides the formation of logical zero levels on bus 12 through open information transistors i and 2.. Therefore, if there is a logical unit level on bus 16, the element implements the logic function f cx ,, X2, where X X C are the arguments corresponding to the logic levels on the first 14, second 15 information buses, and, bus 16, the forward control signal. If there is a logical zero level at the pin 16, and the logical unit level 17 is open on the bus 17, the second 10, the commuting 10 and the second 8 blocking transistors. Combinations of input logic signals 01, 10g 11 ensure the formation of a logical zero on bus 12 through open information transistors respectively 2, 1, 1 and 2. Combination 00 through Open load transistors 4 and allows the formation of lio unic unity on bus 12. Thus, if the bus has a 16. level zero logic element, it implements a logic function, vc Generalized function F, performed by the element v; (vc. When using the control input as an information element, it implements either the function SJ-JE, Bo ZILI-NOT function. The technical and economic effect of using a multifunctional logic element on complementary MOSFETs is to increase reliability by reducing the number of transistors in the device.

Claims (1)

MULTIFUNCTIONAL LOGIC ELEMENT ON MOSFET TRANSISTORS, containing the first, second information and first switching transistors of η type, connected in series, the first, second load transistors of p type, connected in series, two information buses, buses of direct and inverse control signals, drain of the first. ή-type information transistor is connected to the common bus, the drain of the first p-type load transistor is connected to the power supply bus, the gates of the first η-type information and the first load r pa transistors are connected to the first information bus, the gates of the second information η-type and the second load p-type transistors are connected to the second information bus, and the gate of the first p-type switching transistor is connected to the bus of the direct control signal, characterized in that, with In order to increase reliability, a second f> -type switching transistor is introduced into it, which is connected in series with the first and second p-type load transistors, the first p-type and the second η-type blocking transistors, the third ρ-type and four a η-type switched transistor, the drain of the first p-type blocking transistor is connected to the power supply bus, the sources of the first, fourth η-type and second, third p-type switching transistors are connected to the output bus, the drain of the second blocking transistor is connected to the common bus η-type transistor,, the drain of the first p-type blocking transistor is connected to the drain of the second p-type switching transistor, the drain of the third p-type switching transistor is connected to the drain of the second p-type load transistor, the fourth a n-type switching transistor is connected to the drain of the second n-type information transistor, the source of the second l-type blocking transistor is connected to the drain of the η-type switching transistor, the gate of the second p-type switching transistor is connected to the direct control bus, the gates of the first p-type, second l-type interlocking third p-type, fourth η-type switching transistors are connected to the bus of the inverse control signal *. se