SU1287267A1 - One-digit comparator based on insulated-gate field-effect transistors - Google Patents

Abstract

The invention relates to a pulse technique. It can be used in the development of universal digital computers. The aim of the invention is to increase reliability by simplifying. Introduced 1 / new functional relationships, which allowed to achieve the goal. The efficiency of the device in comparison with the prototype lies in the fact that it contains two transistors less. In addition, the proposed device dissolves electrically input and output signals, i.e. does not use bidirectional key elements, which increases the load capacity. 1 il.

Description

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The invention relates to a pulse technique and can be used in the development of universal digital computers.

The aim of the invention is to increase reliability by simplifying.

The drawing shows a schematic diagram of the device.

A one-bit comparator on MIS-transistors contains a successive chain of the first and second transistors 1.2 of the first type, to the drain of the second transistor are connected the drain of the retigo and the fourth transistors 3, 4 of the second type, respectively, fifth in 5

the first transistors 5, 6 of the first type are connected in series, the drain of the sixth transistor 6 is connected to the drains of the seventh, eighth transistors 7, 8 of the second type, the sources of the first, fifth transistors 1, 5 are connected to the first power line 9, the sources of the third, eighth transistors 3, 8 are connected to the second power supply bus 10, the drains of the second and sixth transistors 2, 6 are connected to the first and second output buses 11, 12, respectively, the gates of the first, fourth transistor 1s are connected to the first input bus 13, the gates of the fifth, seventh transistors 5, 7 podkl Yucheny to the second output bus 14, the second jets of the third and sixth, eighth transistors 2, Ze 6, 8 are connected in pairs to the sources of the ninth 15, the ten of the 16 transistors of the second type are connected to the second bus 10 of the power transistors 15; 16 are connected to the first to the second input buses 13, 14, and the drains of the ninth and tenth transistors i5j 16 are connected to the sources of the fourth and seventh transistors 4, 7, respectively, the third output bus 17 is connected to the gates of the sixth, eighth transistors 6, 8, sources The first 9 ninth transistors 1, 15, the fourth output bus 18 podtyuchena to the gates of the second, third transistors 2, 3 and drains of the fifth and ten transistors 5.16,

The device works as follows.

On ghans 9, 10 are connected plus and. minus power sources respectively. Potential plus and VraHyca power source accept72

1 and O, respectively. Input signals are fed to buses 13 and 14. In transistors 1, 15 and 5, 16 inverters are formed for these signals with output buses 17, 18. At the same time, transistors 1 and 5 are transistors that enter into the circuit of the elements OR-NOT with the output buses 11, 12. The transistors 4, 7 are designed DD1Y isolation of the corresponding inverters and elements OR-NOT. If we take the signals coming respectively to buses 13 and 14, in logical designation for signal A and B, then

..

tires 11 and 12 will perform the functions of A. B. and A. B.

The proposed device contains two transistors less than known. In addition, the proposed device dissolves electrically input and output signals, i.e. does not use bidirectional key elements, which increases the load capacity of

Claims (1)

Invention Formula A one-bit comparator on MOS transistors, containing a series of first and second transistors of the first type, is connected to the drain of the second transistor the third and fourth transistors of the second type, the fifth, sixth transistors of the first type are connected in series, the drain of the sixth transistor is connected to the drains of the seventh, eighth transistors of the second type, the sources of the third and eighth transistors are connected to the second power bus, the drains of the second and sixth transistors are connected to the first and the second output buses, respectively, the gates of the first and fourth transistors are connected to the first input bus, the gates of the fifth and seventh transistors are connected to the second input bus, the gates torogo, third, sixth and eighth transistors are connected in pairs, the sources of the ninth and tenth transistors of the second type are connected to a second power bus, The gates of the ninth and tenth transistors are connected to the first and second input buses, respectively, characterized in that, in order to increase reliability, the drains The ninth and tenth transistors are connected to the sources of the fourth and seventh transistors, respectively, a third output bus is connected to the gates of the sixth and eighth transistors and to the drain of the first and ninth transistors, and the output bus is connected to the gates of the second and third transistors and the drain of the fifth and tenth ones transistors.