SU1223223A1 - Carry generator - Google Patents

Abstract

The invention relates to computing and can be used in the construction of multi-bit adders on MOS transistors as an accelerated transfer circuit. The aim of the invention is to increase the speed by reducing the capacities recharged during the switching process. A shaper containing an even number of bits of formation of bitwise transfer, each of which contains the first, second, and third p-type MOSFETs, the first, second, and third M-type transistors of the P-type -type, fourth n-type MOSFET, and an even number of reference elements. Each element of the formation of bitwise transfer can operate in two modes; the mode of formation of bitwise transfer and in the mode of formation of through transfer. The corresponding mode is determined by the combination of the signals at the inputs of the corresponding bits of the terms. I il. YO YO SO SO YOU GCHE SO

Description

The invention relates to computing and electronics and can be used in the construction of arithmetic logic devices for processing digital information, in particular in the construction of multi-digit adders as a driver for accelerated transfer.

The purpose of the invention is to increase the speed of the transfer former.

The drawing shows the functional diagram of the transfer driver.

The transfer driver contains the first, second and third MOSFET transistors 1-3 of p-type, the first, second, third MOSFET transistors of 4-6 p-type, the fourth MOSFET transistor of 7 p-type, the fourth MIS transistor 8 of the p-type, which form the unit of formation of bitwise transfer, the elements of 10 comparison, the outputs and elements of the formation of bitwise transfer, the power supply line 12, the zero potential bus 13, the inputs 14 of the corresponding bits of the first term, the inputs of the 15 corresponding bits of the second term , inverse inputs of 16 corresponding ra The views of the first term, the inverse inputs 17 of the corresponding bits of the second term, the transfer inputs 18 of the elements 9 of the formation of bitwise transfer.

The transfer driver works as follows.

Each element of the formation of bitwise transfer 9 can be in two modes: in the mode of forming its own transfer and in the mode of forming through transfer. The corresponding mode is determined by a combination of signals at the direct inputs 14 and 15 of the components. If the signals at the indicated inputs 14 and 15 (own transfer) coincide, the comparison element 10 generates at its forward and inverse outputs; respectively, high and low levels, opening the second MOSFET transistor 5 p-type, the second MOSFET transistor 2 p-type and locking the fourth 7 and fourth 8 MOSFET transistors, respectively, p-type and p-type bit 9 transfer. If low levels are set up at inputs 14 and 15, the first M-transistor 1 is p-type and the first MOS-transistor 4 is n-type, and a current flow channel is formed between the power bus 12 and the output 11, which ensures the formation of 11 high level Installation at the inputs 14 and 15 of high levels leads to the formation of the opposite (low) level at output 11 through the open first MOSFET 4 n-type and the second MOSFET 5 n-type.

If the signals at inputs 14 and 15 (through transfer) do not coincide, the comparison circuit 10 generates at its forward and inverse outputs, respectively, low and high levels, which open the fourth MOSFET 7 of the p type and the fourth: the third MOSFET of 8 p- type and locking the second MOSFET transistor 2 is p-type, and the second MOSFET is 5 n-type, which ensures the formation at output 11 of element 9 of forming bitwise signal transfer inverse to the signal at input 18 of element 9. Thus, every 0 odd element of formation transference 9 implements the logical formula

, 5УХ, 4ЛХ, 8УХ, 5ЛХ, 8,

5 where Хм, Х | 5 - logical values of direct signals at the inputs of the terms; Xi8 is the logical value of the forward carry signal from the previous bit.

Similarly, each even element 9 of the formation of bitwise transfer implements the logical formula

Fn (X, 4AX, 5VX, 4AX, 5) V (X, 4AX, 5V HOX | 4LH, 5) AH | BAH, 7,

where X | b, Xi7 - logical values of the inverse signals at the inputs of the terms

Taking into account that, we get

° Re X, 4АХ, 5УХмАХ, 8УХ, 5АХ, 8.

Thus, at the outputs of odd elements 9 of forming bitwise transfer, inverse bitwise transfers are formed, and at the outputs of even elements of bitwise formation 9 are direct bitwise transfers, and, since the shaper contains an even number of elements of 9 of bitwise transfer, Shaper Outlet - Direct Transfer.

Claims (1)

Invention Formula A transfer driver containing an even number of bitwise transfer elements, each of which contains the first, second and third MIS transistors of the p-type and the first, second and third MOS transistors of the p-type, and the drain of the first MOS transistor of the p-type and the drain of the first p-type MOSFET is connected respectively to the source of the second p-type MOSFET and the source of the second p-type MOSFET, the source of the first p-type MOSFET is connected to the power bus, the source of the first MOSFET n -type - with a zero potential potential, s creates the first MIS transistor of p-type element forming each odd bit-wise the transfer is connected to the inputs of the corresponding bits of the first addend of the transfer generator, characterized in that, in order to increase speed, a fourth p-type MOS transistor and a fourth p-type MOS transistor and an even number of comparison elements, whose inputs connected to the inputs of the corresponding bits of the first and second terms, the fourth p-type MOS transistor and the fourth p-type MOS transistor are connected by sources to buses, respectively, of power and zero potential, and drains to sources, respectively, tr the third p-type MOS transistor and the third p-type MOS transistor, the gates of which are the input of this bit transfer formation element and are connected to the output of the previous bit transfer formation element, the second n-type MOS transistor and the fourth MOS transistor the p-type transistor is connected to the direct outputs of the reference element, the gates of the second p-type MOS transistor and the fourth m-transistor of the n-type are connected to the inverse outputs of the reference element, the gates of the first MIS transistor The n-type sources of each even-numbered transfer unit are connected to the inverse inputs of the corresponding bits of the transfer driver, the drains of the second and third p-type MOSFETs, the second and third M-type np transistors transfer and connected to the input of the subsequent element of the formation of bitwise transfer. tii-f . I 1 Pi Р1 „- 18 tl l ff -Lj aha ff tak-jb