SU1008909A1 - Insulated gate field-effect transistor based adder - Google Patents

Description

11 The invention relates to electronics and computing and can be used in the construction of arithmetic devices. A half-adder is known that contains 7 p-type MIS transistors lj. The disadvantage of this element is the increased power consumption due to the fact that the device is made on transistors of the same type 1 A half-adder on MOS transistors is known, containing the first, second third and fourth MIS transistors of the p-type and fifth, sixth, seventh and the eighth MOSFET type 1 transistors, with the drains of the first, third and fourth transistors connected to the fifth, sixth and seventh drains, the drain of the second transistor, respectively, connected to the output bus and. the drain of the sixth transistor, the gates of the first and pt transistors are connected to the first input bus, the fourth and seventh to the second, one third of it and the sixth to the drains of the fourth and seventh, second and eighth to the first and second transistors of the sources of the first, second, the third and fourth transistors are connected to the power bus, the source of the second transistor is connected to the second input bus, the source of the sixth is connected to the drain of the eighth, the source of the seventh transistor is connected to the first input bus, the source of the eighth transistor is to the common bus, 2. A disadvantage of the known element is the low response rate due to the connection. the fact that the charge of the capacitance formed by the drains of the first and fifth fourth and seventh pairs of transistors through the fifth and seventh open transistors with the combination of input signals A 1, B 1 takes place only dp level E-iprr where E POR t where level eg the threshold voltage of the tt-type transistor, (-effect of the influence of the substrate of the f-type and the specified level is less than level 1. Thus, the voltage levels of the sixth and eighth transistors are lower than the voltage level 1 what leads to an incomplete unlocking of the latter, thereby, k an increase in the formation time at the output voltage not equal to the voltage corresponding to 0. The purpose of the invention is to increase the speed of the device.The goal is achieved, which is in a half-adder on MIS transistor containing the first., the second, the third and fourth, sixth, seventh and seventh MOSFET transistors, while the drains of the first third and fourth transistors are connected respectively to the drains of the fifth, sixth and eighth transistors, the drain of the second razistor You are a connected to the first. one bus, the gates of the first and fifth transistors are connected to the first input bus, the fourth and seventh to the second, third and sixth to the drains of the fourth and seventh transistors, the source of the second transistor is connected to the source of the third transistor, and the drain of the fourth to the power bus, . The ninth MIS transistor is inserted. P-type, with the sources of the first, sixth and gates of the second, ninth transistors connected to the second bus, the sources of the eighth, ninth, second and third transistors are connected to the first input bus, the source of the seventh to the common bus, the gate of the eighth and the source of the second to the gate of the third transistor, the drains of the first and second transistors are connected to the drain of the eighth, and the drains of the ninth, sixth and third transistors to the second output bus. The drawing shows an electrical schematic diagram of the proposed device. The device contains MTD-transistors 1-4 p-type and MOS transistors 5 9 p-type. The drains of the first, third and fourth transistors are connected respectively to the drafts of the fifth, sixth and seventh. The gates of the first and pt transistors and the sources of the second and third, eighth and ninth transistors are connected to the first input bus.10, which receives the input signal A. The gates of transistors 2, 9, 4 and 7 and the sources of transistors 1, 6, 7 are connected to the second input bus 11, to which the input signal B is fed. The source of the transistor is connected to the power bus 12, and the source of the transistor 7 to the common bus 13. The drains of transistors 1, 2, 5 and 8 are connected to the first output bus 14, on which a signal is formed cash S. Drains of transistors 3, 6 and

9 are connected to the second output bus 15, on which the signal P. is generated.

The device works as follows.

When the combination of input signals A 0, V O closed transistors

1 and 5 and through open transistors

2 and 8 on the bus And the signal is formed S Oh through the open transistor 6

a signal is formed on the bus 15-P 0 When the input signals A 0, B 1 are combined, the second, fifth and eighth transistors are closed and the signal S-1 is formed on the bus 14 through the open transistor 1, the signal P 0 is generated on the bus 15 the third and ninth transistors,, the transistor 6 is closed. With

combinations of the input signals А 1, В О closed the first, seventh, ninth AND third transistors. The signal S 1 on the bus I is formed through the open second and eighth transistors, and on the bus 15 a signal P O is formed through the open transistor 6. When the input signals A 1, B - 1 are combined, the first, second, fourth, sixth are closed. and eighth transistors. On the bus H, a signal is generated through the open transistor 5. On the output bus 15, a signal P 1 is generated through the open transistors J and 9.

i

The work of the half-adder illustrates

with table

 the table follows, output C is realized by function S AB +, and output 15 P. The use of the proposed device increases the speed by increasing the voltage of logic levels, improves the overall speed of arithmetic devices. Machine simulation shows that the speed of the proposed device is higher than the speed of a known device by 30. In addition, there is no need to use additional elements to implement the function of bit transfer when building complete adders.

Claims (1)

(5 * 0 SEMI-SUMMATOR ON MOSFET TRANSISTORS, containing the first, second, third and fourth MOSFET p-type transistors and the fifth, sixth, seventh and eighth MOSFETs of the p-type, 'while the drains of the first, third and fourth transistors are connected respectively, to the drains of the fifth, sixth and seventh transistors, the drain of the second transistor is connected to the first output bus, the gates of the first and fifth transistors are connected to the first input bus, the fourth and seventh to the second, third and sixth to the drains of the fourth and seventh transistors, the source of the secondthe transistor is connected to the source of the third transistor, and the source of the fourth * · to the power bus ^; characterized in that, in order to improve performance, the ninth η-type MOS transistor is introduced into it, and the sources of the first, sixth and the gates of the second, ninth transistors are connected to the second input bus, the sources of the eighth, ninth, second and third transistors are connected to the first input bus, the source of the seventh to the common bus, the gate of the eighth and the source of the fifth to the gate of the third transistor, the drains of the first and second. of the first transistors are connected to the drain of the eighth, and the drains of the ninth, sixth and third transistors are connected to the second output bus.