SU1019635A1 - Level converter - Google Patents

Abstract

LEVEL TRANSMITTER, containing the elements AND-YE, OR-HB, the first inputs of which are connected to the information bus, the second - to the first and second buses of the control signals, respectively, and the outputs, respectively, to the gates of p-channel and p-channel MOS transistors connected in series between the first power bus and the common bus, the drains of which are connected to the output bus, are from that, in order to simplify the device, a second NAND cell is additionally inserted into it, the direct input of which is connected to the element output AND-NOT, INV rsny input - to the output of NOR IZSH element, and an output - to a gate of the additional p-channel MOS transistor, vklnzchennogo shinsL between the second power and output shinsyy, the substrate of which is connected to the first bus | nutrition (L 9 9 / J

Description

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This invention relates to microelectronics and can be used as an output element in an LSI based on MOS transistors.

The converters are known, allowing to form at the output of a level 5 logical O, logical and disconnected state. They contain AND-NOT, OR-NOT and sequentially® elements connected between the p-channel 10 and n-channel MOS transistors 1 power buses.

The disadvantage of these devices is that an external resistor connected between the output bus and the power bus or a common bus is required to determine the logical state of the output. This leads to a deterioration of the electrical parameters of the device and requires additional space for arranging the resistor.

A level converter is known, which contains the elements AND-NOT, OR-NOT, the first ones were entering the WHAT "X are connected to the information bus, the second to 55 first and second buses of control signals, respectively, and the outputs respectively to the gates of p-channel and p-channel MOS transistors connected in series between the first bus to the output bus. The substrate of the p-channel transistor is connected to the common bus and the substrate of the p-channel transistor to the second power bus. Parallel to the p-channel transistor, an additional n-channel MOS transistor is connected, in which the substrate is connected to the output bus and the gate through the inverter to the gate of the p-channel transistor 2.

A disadvantage of the known converter is the difficulty of realizing, due to the presence of the connection of the substrate of an n-channel additional MOP-45 transistor to the output bus, which requires a large number of technological operations with an integral design. .

The purpose of the invention is to simplify the integral CQ device.

In order to achieve this goal, a level converter containing elements NAND, NOR or NOT, the first inputs of KOTOEftix are connected to the information bus 55, the second to the first and second buses of control signals, respectively, and the outputs respectively to the gates p- channel and p-channel MOSFET transistors connected in series between the first power bus and the common bus, the drains of which are connected to the output uine, are additionally introduced a second AND-NE element whose direct input, 5

connected to the output of the NAND element, the inverse input to the output of the element OR NONE, and the output to the gate of an additional p-channel MOS transistor connected between the second power bus and the OUTPUT bus, the substrate of which is connected to the first power bus.

The drawing shows an electrical schematic diagram of the device.

According to the scheme, the first input of the NAND 1 element and the first input of the OR-NOT 2 element are connected to the information bus 3, the second inputs are connected to the first 4 and second 5 control signals, respectively, and the outputs respectively to the p-channel gates 6 and n -channel 7 MOSFETs connected in series between the first power supply bus 8 and the common bus 9, the drains of which are connected to the output bus 1.0. The direct input of the additionally introduced second element IS-NE 11 is connected to the output of element 1, and the inverse input is connected to the output of element 2, the output of element 11 is connected to the gate of the additional p-canadian MOSFET 12 connected between the second power bus 13 and bus 10 whose substrate is connected to the first power bus 8.

The device works in the following way.

When a logical zero and voltage are applied to the information bus 3 on buses 4 (logical) and 5 (a logical output is formed at the output of the converter. When entering the logical bus 3 and 4, the transistor b opens, at the output of the converter, a logic is formed corresponding to the level of the power supply bus 8. In the absence of enabling signals on the buses 3 and 4, the transistors 6 and 7 are closed, the output of the AND-NE element 11 forms the logical level O, the MOSFET 12 is opened and at the output of the converter, a third logic level is formed corresponding to the potential level on the bus 13.

The proposed converter as compared with the known one has a number of technical and economic advantages: due to the inclusion in the converter of a second p-channel transistor instead of an n-channel transistor, there is no connection between the substrate of the n-channel transistor and the output bus, which is very complex in implementation

31019635,

and requires additional state-of-the-art technology,), due to the lack of overall dimensions due to the lack of overall dimensions of the resistor device, which is additionally determined.

Claims (1)

LEVEL CONVERTER, “containing AND-NOT, OR-NOT elements, the first inputs of which are connected to the information bus, the second to the first and second bus of the control signals, respectively, and the outputs, respectively, to the gates of the p-channel and p-channel MOS transistors, connected in series between the first power bus and the common bus, the drains of which are connected to the output bus, from which they are connected so that, in order to simplify the device, a second AND-NOT element is added to it, the direct input of which connected to the output of the element AND NOT, inv The rs input is to the output of the OR-NOT element, and the output is to the gate of an additional p-channel MOS transistor connected between the second bus and the output bus, the substrate of which is connected to the first power bus. with FO SL J>