SU1474831A1 - G-flip-flop - Google Patents

Abstract

The invention relates to a pulse technique and can be used to indicate the end points of parallel transients. The purpose of the invention is to increase reliability by reducing the number of transistors used and their connections. The G-flip-flop contains inputs 9, (N + 1) CMOS inverters 1 and 4, resistor 5, P-transistor 7, N-transistor 6, output 8. The device switches to an alternative state with equality (alternative to the previous one) log. levels on all inputs 9. The operation of the G-flip-flop in this mode is described in the materials of the invention. 1 il.

Description

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The invention relates to a pulse technique and can be used to indicate the end points of parallel transients.

The purpose of the invention is to increase the reliability of the G-flip-flop by reducing the number of elements used (inserting a resistor and a MOSFET transistor allows replacing the OR-NOT element with an output inverter, which saves equipment).

The drawing shows a schematic diagram of the G-trigger.

The G-Trigger contains input CMOS inverters 1, each of which consists of two MOS transistors 2 n-ti and 3 p-type, output inverter 4, resistor 5 and the second and first p-type MOS transistors type 7, the output of the inverter 4 is connected to the output of the 8 G-trigger and the gates of the second 6 and first 7 MOS transistors, sources

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20 this, due to the connection between the output of the inverter 4 and its input through the resistor 5, the potential ia of the input of the inverter 4 will increase, and at its output decrease until

which are connected respectively to the common bus and the power bus, and the drains 25 are opened by the transistor 7, after which the inverters 1 are installed to the common input and the power input of the inverter 4, i.e. their transiscal potential is their origins, and at its output, tori 2 and 3, the gates of which are connected, i.e. output 8 G-flip-flop, - low us with the input of the inverter 1, and drains - with

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Its output, the inputs of inverters 1 are connected to the inputs of 9 G-flip-flop, and the outputs - to the input of inverter 4 and through a resistor 5 - to the output of an 8-G flip-flop.

G-Trigger works as follows.

Suppose that initially on all the inputs of the 9 G-flip-flop there are low potentials P and at its exit 8 there is also a low potential. In this case, the transistors 3 of the inverters 1 and the transistor 7 are open, and the transistors 2 of the inverters 1 and the transistor 6 are closed, i.e. At the input of the inverter 4 there is a high potential, which makes the indicated state of the G-trigger stable until at least one of its inputs 9 has a low potential and the transistor 3 of the corresponding inverter 1 is open.

If on all inputs 9 G-trigger

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If the potentials are high, the transistors 3 of the inverters 1 will close, and their transistors 2 will open. In this case, due to the connection between the output, the inpotential which will close the transistor 6 and the G-trigger will be in the initial state.

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Claims (1)

Invention Formula A G-Trigger containing n inputs connected respectively to the inputs of the n inverters, the power supply bus and the common busbar of which are respectively combined, the first and second MOS transistors, the gates of which are connected to the output, the power bus and the common bus, characterized in that increase in reliability, an output inverter and a resistor are introduced into it, the source of the first p-type MOSFET is connected to the power supply bus, the drain is connected to the power supply wires of n inverters, the common buses of which are connected to the drain of the second n-type MOSFET transistor, the source of which is connected to total w the other, the outputs of all n inverters are connected to the input of the output inverter and the first output of the resistor, the output of the output inverter and the second output of the resistor are connected to the output bus. 4748312 the driver 4 and its input through the resistor 5 at the input of the inverter 4 the potential will decrease, and at its output - increase until the transistor 6 opens, after which a low potential is established at the input of the inverter 4 and so on. e. output 8 G-flip-flop, - high potential, which closes the transistor 7. This state of the G-flip-flop is stable as long as one of its inputs 9 has a high potential and transistor 2 has the corresponding 15 Inverter 1 will open. If all the inputs of the 9 G-flip-flop have low potentials in the TC, then the transistors 2 of the inverters 1 will close, and their transistors 3 will open. With 20 this, due to the connection between the output of the inverter 4 and its input through the resistor 5, the potential ia of the input of the inverter 4 will increase, and at its output decrease until 25, transistor 7 will open, after which a high potential will be established at the input of inverter 4, and at its output, i.e. output 8 G-flip-flop, - low transistor 7 will open, after which a high potential will be established at the input of inverter 4, and at its output, i.e. output 8 G-flip-flop, - low the potential that transistor 6 closes and the G-flip-flop will be in the initial state. five 0 five 0 Invention Formula A G-Trigger containing n inputs connected respectively to the inputs of the n inverters, the power supply bus and the common busbar of which are respectively combined, the first and second MOS transistors, the gates of which are connected to the output, the power bus and the common bus, characterized in that increase in reliability, an output inverter and a resistor are introduced into it, the source of the first p-type MOSFET is connected to the power supply bus, the drain is connected to the power supply wires of n inverters, the common buses of which are connected to the drain of the second n-type MOSFET transistor, the source of which is connected to total w the other, the outputs of all n inverters are connected to the input of the output inverter and the first output of the resistor, the output of the output inverter and the second output of the resistor are connected to the output bus.