SU1471306A1 - Voltage converter using cmos transistors - Google Patents

Abstract

The invention relates to the field of pulsed technology and can be used to match TTL circuits with integrated circuits on CMOS transistors. The purpose of the invention is to enhance the functionality and increase speed. The device contains two inverters of 1, 2 and twelve transistors. By connecting the source of the ninth transistor 12 to the input bus 15 and cross-connecting the gates and drains of the eleventh and twelfth transistors 16 and 17, the range of transformable voltages is expanded. The separate control of the third and eleventh transistors 6, 16, and the fourth and twelfth transistors 7, 17 allows for an increase in speed. 1 il.

Description

four

00

about a

The invention relates to a pulse technique and can be used to match TTL circuits with integrated circuits in CMOS transistors.

The purpose of the invention is to expand the functionality by expanding the range of input voltages of the levels being converted and increasing the speed.

The drawing shows a schematic diagram of the converter.

The voltage level converter on CMOS transistors contains two inverters 1 and 2 connected between the common bus and the first bus 3 -power, and twelve transistors, the outputs of the first and second inverters 1 and 2 are connected to the gates of the first and second transistors 4 and 5 s channels of the first conductivity type respectively, the inputs of inverters 1 and 2 are connected to the drains of the third and fourth transistors 6 and 7 with the channels of the first conductivity type, respectively, the sources of the first, second, third, fourth, fifth and sixth transistors 4-9 with The channels of the first conductivity type are connected to the power bus, the drains of the first and second trasls 4 and 5 are connected to the sources of the seventh and eighth transistors 10 and 11, respectively, with channels of the first conductivity type whose drains are connected to the third, fifth, eighth, fourth, sixth and seventh

17 and 16 and the inputs of inverters 1 and 2, respectively.

The converter works as follows.

In the initial state, the voltage at the input 15 corresponds to level 1. Then the transistors 5,7,9,13 and 16 are open, the transistors 4,6,8,11,12 and 17 0 are closed at the gate, the transistor 10 is closed at the source, the voltage at the input of inverter 1 is O, and at the input of inverter 2 is 1 - 1.

When changing to input power

15 15 1 to O transistor 12 opens, and transistor 13 closes, the specific steepness of transistors 12 and. 13 is chosen significantly more than the steepness of transistors 8 and 9, which

20 are needed to hold state 1 at the gates of transistors 7 and 6, therefore, the voltage across the gate of transistor 6 switches to the state O rather quickly, transistor 6

25 opens, the transistor 17 opens, the transistor 16 closes, after a time determined by the delay of the inverters 1 and 2, the transistor 4 opens, and the transistor 5 closes.

30 The voltage at the input of the inverter 1 is held by the open transistor 6, and at the input of the inverter 2 by a transistor 17.

35

Operation of the converter when changing the voltage on its input from 0 to 1 occurs in a similar way.

I Connect the gate of transistor 12 and the source of transistor 13 to the bus. 14, the second voltage source E2, the gate of the transistor 13 and the source of the transistor 12 to the input 15 provides signal conversion in a wide range of input voltages.

to high UIH levels of care signal transistors 6, 8, 11, 7, 9 and 10, respectively, the drains of the fifth and sixth transistors. Q resistors 8 and 9 are connected to the gates of the seventh and eighth transistors 10 and 11, respectively;

12and the source of the tenth of that 13 transistors

connected to the second bus 14 of the power supply, with only the following limit imposed ;; of that transistor 12 and of the voltage: (1) - to a low UIL, and (2) - the thief of the ten transistor 13 with the channels of the second type of conductivity connected to input bus 15, the drains of the ninth and tenth transistors 12 and ".

13 are connected to the drains of the seventh and ... eighth transistors 10 and 11, respectively, the sources of the eleventh and twelfth transistors 16 and 17 with the channels of the second conductivity type are connected to the common bus. Drains one-, twelfth and twelfth transistors

55

1b th 17 are connected to the gates of the twelfth and eleventh transistors

Nala, namely

UIH E2-U01; (1) UIH - U02, (2) where UOl, U02 are the threshold voltages of the transistors of the first and second conduction types, respectively. ), On bus 14, it is necessary to apply a reference voltage equal to

m-t.m (3)

The speed and sensitivity of the converter increase significantly4713062

17 and 16 and the inputs of inverters 1 and 2, respectively.

The converter works as follows.

In the initial state, the voltage at the input 15 corresponds to level 1. Then the transistors 5,7,9,13 and 16 are open, the transistors 4,6,8,11,12 and 17 0 are closed at the gate, the transistor 10 is closed at the source, the voltage at the input of inverter 1 is O, and at the input of inverter 2 is 1 - 1.

When changing to input power

15 15 1 to O transistor 12 opens, and transistor 13 closes, the specific steepness of transistors 12 and. 13 is chosen significantly more than the steepness of transistors 8 and 9, which

20 are needed to hold state 1 at the gates of transistors 7 and 6, therefore, the voltage across the gate of transistor 6 switches to the state O rather quickly, transistor 6

25 opens, the transistor 17 opens, the transistor 16 closes, after a time determined by the delay of the inverters 1 and 2, the transistor 4 opens, and the transistor 5 closes.

30 The voltage at the input of the inverter 1 is held by the open transistor 6, and at the input of the inverter 2 by a transistor 17.

Operation of the converter when changing the voltage on its input from 0 to 1 occurs in a similar way.

I Connect the gate of transistor 12 and the source of transistor 13 to the bus. 14, the second voltage source E2, the gate of the transistor 13 and the source of the transistor 12 to the input 15 provides signal conversion in a wide range of input voltages.

to a high UIH level of care signal, with only the following limitations: (1) to a low UIL and (2) -

however, the following restrictions are imposed: (1) - on low UIL and (2) -

Nala, namely

UIH E2-U01; (1) UIH - U02, (2) where UOl, U02 are the threshold voltages of the transistors of the first and second conduction types, respectively. ), On bus 14, it is necessary to apply a reference voltage equal to

m-t.m (3)

The speed and sensitivity of the converter increases significantly if the bus 14 is given a signal inverse to the input signal on the bus 15. At the same time, the amplitude of the input signal, i.e. the difference between the high and low input voltages should exceed the threshold voltage of a transistor of the second conductivity type.

From expressions (2) and (13), it is also expected that the converter maintains its operation in a wide range of changes in threshold voltages, up to negative values of U02, which ensures the expansion of its functional capabilities.

Claims (1)

Invention Formula A voltage level converter on CMOS transistors containing two inverters connected between a common bus and the first power bus and twelve transistors, the outputs of the first and second inverters are connected to the gates of the first and second transistors with channels of the first type of conductivity, respectively, the inverter inputs are connected to the drains of the third and fourth transistors with channels of the first conductivity type, respectively, the sources of the first, second, third, fourth, p the sixth transistors with channels of the first conductivity type are connected to the first power line, the drains of the first and second transistors are connected to the sources of the seventh and eighth transistors with channels of the first conductivity type, respectively, whose drains are connected to the gates of the third, fifth, eighth and fourth, sixth, seventh transistors respectively, the drain of the fifth and sixth transistors are connected to the gates of the seventh and eighth transistors, respectively, the ninth, and the source of the tenth transistors of the second type of wire They are connected to the second power bus, the drains of the ninth and tenth transistors are connected to the drains of the seventh and eighth transistors, respectively, the sources of the eleventh and twelfth transistors with channels of the second conductivity type are connected to a common bus, so as to expand the functional possibilities and speed, the drains of the eleventh and twelfth transistors are connected to the gates of the twelfth and eleventh transistors, respectively, the tenth gate and the source of the ninth transistor trench are connected to the input bus.