SU818015A1 - Device for matching ttl-circuits with mds-integrated circuits - Google Patents

Description

(54) DEVICE OF AGREEMENT OF TTL SCHEMES WITH TIR INTEGRAL SCHEMES

the thief of the n-channel transistor of the second inverter is connected to the gate of the n-channel transistor of the first inverter, the output of which is connected to the gate of the n-channel transistor of the third inverter, the gates of the p-channel transistors of the second and third inverters are connected to the outputs of the third and second inverters . the source of the n-channel transistor is connected to the negative voltage source bus, the gate is connected to the output of the first inverter, the drain is connected to the gate of the n-channel transistor of the first inverter and the drain of the p-channel transistor whose gate is connected to the zero potential bus, and the source to the input device and drain input transistor.

The drawing shows a circuit diagram of a device for matching TTL circuits with MOS integrated circuits, performed on additional transistors.

The device contains an input transistor 1, the first inverter transistors 2 and 3, the second and third inverters transistors 4-7, two series-connected transistors 8 and 9, the device input 10, the first and second outputs 11 and 12 of the device, the output 13 of the first inverter, point 14 of the connection of two series-connected transistors, the bus 15 of the negative voltage source (-E |), the bus 16 of the first source of positive voltage (+ E.), the bus 17 of the second source of positive voltage (+ Ez) 17, the bus 18 of zero potential. ,

Input transistor 1 is designed to increase the level of logic "1 at the input of the device.

The device works as follows.

Suppose, in the initial state, the level at the input 10 of the device corresponds to the logical one. “1. When this transistor 3 is closed, and the transistor 9 is open. At points 13 and 14, the values of the stresses are close to the stresses m-Ei and + Ez, respectively. These voltages are applied to the gates of the transistors 4 and 6, which are respectively in the open and closed states. The potentials at the outputs 11 and 12 will be equal to -El and -e. Due to the action of the input transistor 1, the voltage at the input 10 of the device is set close to the supply voltage + Ez, ensures reliable closing of the transistor 3.

Upon arrival at the input 10 of the logical device O, the transistor 3 opens and the transistor 9 closes. The transistor 2 is still open and forms a voltage divider with the transistor 3, the voltage at point 13 of which is determined by the ratio of the steepness of transistors 2 and 3. With the correct choice of the steepness of transistors 2 and 3, the voltage at point 13 must ensure the opening of transistor 8, which leads to voltage change at point 14. This voltage change is transmitted to the gate of transistor 2 and it closes, the voltage at point 13 increases.

The process of opening the transistor 8 and closing the transistor 2 proceeds as an avalanche until the voltage at point 14 reaches a value close to - EI. At the same time, transistor 2 closes and at point 13 a voltage close to + E3 is set and transistor 4 closes at the same time and transistor 6 opens. With an appropriate choice of the slope of transistors 4-7, the voltages close to + EZ and - E |.

Switching the device to the opposite state occurs in the same way.

The introduction of two successively connected HeHiftix transistors expands the functionality of the proposed device, since it makes it possible to match TTL circuits with MIS integrated circuits on auxiliary transistors powered from different polarity voltage sources .j

Claims (2)

Invention Formula 0 A device for matching TTL circuits with MIS integrated circuits, made on additional MIS transistors, containing an input transistor, the gate of which is connected to the zero potential bus, the source to the first source bus 5 positive voltage, drain to the gate of the p-channel transistor of the first inverter connected between the buses of the first source of positive voltage and the source of negative voltage, the second and third inverters connected between the buses of the second source of positive voltage and a source of negative voltage, gate The n-channel transistor of the second inverter is connected to the gate of the n-channel transistor of the first 5 of the inverter, the output of which is connected to the gate of the n-channel transistor of the third inverter, the gates of the p-channel transistors of the second and third inverters are connected respectively to the outputs of the third and second inverters, characterized by 7, That, in order to extend the functionality, two MOS transistors are inserted into the device, the source of the n-channel transistor is connected to the negative voltage source bus, the gate is connected J to the output of the first inverter, the drain to the gate of the n-channel transistor of the first inverter and the drain of the p-channel transistor, the gate of which is connected to the zero potential bus, and the source to the device input and the drain of the input transistor. Sources of information taken into account in the examination s 1.Patent of France No. 3273921, cl. H 03 K 19/40, 1978. 2. USSR author's certificate number 513502, cl. H 03 K 19/00, 1974 (prototype). 1Z eleven