RU1811002C - Exclusive or gate - Google Patents

Abstract

Usage: the present invention relates to the field of pulse technology and microelectronics and can be used in the construction of digital devices for various purposes, in particular in the construction of control circuits. SUMMARY OF THE INVENTION: an EXCLUSIVE OR element contains five MOSFET elements OR-NOT (1-5), four elements MODULATION TWO (6-9), element 2-2I-2 OR-NOT (10), element 4 -2I-4OR-NOT (11), eight input buses (12-19) and one output bus (20). 5 ill.

Description

ate

with

oh oh

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Figure 1

The invention relates to the field of pulse technology and microelectronics and can be used in the construction of digital devices for various purposes, in particular, in the construction of control circuits.

The purpose of the invention is to simplify the element EXCLUSIVE OR.

In FIG. 1 is a functional diagram of an EXCLUSIVE OR element; in FIG. 2-5 are embodiments of MOS transistors, respectively, of the elements OR-NOT, COMPOSITION BY MODULE TWO, 2-2I-2OR-NOT, and 4-2I-4OR-NOT.

The EXCLUSIVE OR element (Fig. 1) contains five elements OR-NOT 1 ... 5, four elements made on MOS transistors, four elements COMPOSITION BY MODULES TWO b ... 9 element 2-2I-2 OR NOT 10, element 4-2Y-4OR-NOT, eight input buses 12 ... 19, output bus 20.

The OR-NOT element (Fig. 2) is made on two switching 21 and 22 MOSFET transistors connected between the supply lines 24 and 25. The first 26 and second 27 input buses of the element are connected respectively to the gates of the transistors 21 and 22, the output the element bus 28 is connected to the drains of the transistors 21 and 22 (with the source of the transistor 23). . The COMPOSITION MODULE TWO element (Fig. 3) is made on two switching 29 and 30 and three load 31, 32 and 33 MOS transistors connected between the power lines 34 and 35. The first 36 and second 37 input buses of the element are connected respectively to the gates of the transistors 29 and 30, the output bus 38 of the element is connected to the drain of the transistor 32 (with the source of the transistor 30).

Element 2-2I-2 OR-NOT (Fig. 4) is made on four switching 39 ... 42 iodine load43 MOS transistors connected between the power lines 44 and 45. The first 46, second 47, third 48 and fourth 49 input buses of the element connected respectively to the gates of transistors 39, 40, 41 and 42. The output bus 50 is connected to the source of transistor 43 (with drains of transistors 3.9 and 41).

Element 4-2I-4I L AND-NOT (Fig. 5) is made on eight switching 51 ... 58 and one load 59 MOS transistors connected between the power lines 60 and 61. First 62, second 63, third 64, fourth 65, paragraph 66, pole 67, seventh 68 and eighth 69 the input buses of the element are connected respectively to the gates of transistors 51.52.53.54.55.56.57 and 58. The output bus

70 is connected to the source of transistor 59 (with drains of transistors 51, 52, 53, and 54).

The EXCLUSIVE OR element works as follows. The input variables xi ... X8 (in random order) are supplied to the input buses 12 ... 19, the logic function FF (XT, X2, .... xs) is implemented on the output bus 20, which takes a unit value if and only if exactly one unit is present in the input information word x (XL X2, .... xs), i.e.

T, if xi + X2 + ... + X8 1; . Oh, otherwise.

The structure of an EXCLUSIVE OR element is described by the following logical expression:

0 F AoBovCoDo v ApBi v AiBo v CoDt v CiDo, where AO xi v xg; In xs v X4, - With HB v xe;

Do x v xe; AI xi © X2: W xs F W,

5 Ci X5PX6; DI x7fhv.

The advantage of an EXCLUSIVE OR element is its simple construction. So, it consists of 5 two-input elements OR NOT, 4 two-input elements

0 ADDITION BY MODULE TWO, element 2-2I-2OR OR NOT (as a rule, in most valve libraries of LSI / VLSI design, its complexity is equivalent to the complexity of the two-input element COMPOSITION ON MODULE TWO) and element 4-2I- 4OR-NOT. With item 8, the prototype contains 7 two-input elements AND-NOT (the elements are equivalent in complexity to two-input elements OR-NOT) and 7 two-input elements COMPOSITION BY MODULE TWO.

Thus, the EXCLUSIVE OR element requires 49 MOS transistors for its implementation, and the prototype (with clause 8) requires 56 MOS transistors.

5 In addition, the prototype uses an IL element with 7 inputs, the implementation of which as an INSTALLATION OR is difficult in many integrated technologies. Moreover, the prototype has two output buses,

0 by a combination of signals on which the value of the EXCLUSIVE OR function is determined on this set of arguments, which in some cases makes it difficult to use an element (to obtain a single output 5 element, it is necessary to additionally use the FORBID element, which leads to an increase in the circuit depth and prototype complexity).

The indicated advantages of the proposed element over the known result in

high technical and economic efficiency in its implementation by modern integrated technologies.

Claims (1)

SUMMARY OF THE INVENTION An EXCLUSIVE OR element containing four addition elements modulo two, 1- (I 1,2) input j-ro bus (1 1,2.3, 4) of which is connected to the (i + 2x xj -.2) th the input bus of the element is EXCLUSIVE OR, excluding ft, so that, for the sake of simplicity, it contains the element 2-2I-2OR-NOT. element 4-2I-4 OR-NOT and five elements OR-NOT, 1- the input bus j-ro of which is connected to the i-th input bus j-ro of the addition element modulo two, the output bus of which is connected to j- the input bus of element 4-2I-4 OR-NOT, the output bus of which is connected to the first input bus of the fifth element OR-NOT, the output bus of which is connected to the output bus of the EXCLUSIVE OR element, and the second input bus is connected to the output bus of element 2 -2I-2 OR-NOT, J- the input bus of which is connected to the output bus j-ro of the OR-NOT element, the output bus (3 - i) -ro of the OR-N element connected to the (i + 4) th input bus of the element 4-2I-4 OR-NOT, (1 + 6) - the input bus of which is connected to the output bus of the (5 - 1) th element OR-NOT, the OR element does NOT contain three MOS transistors, the gate of the first of which is connected to the i-th input line of the element, and the source is connected to the first power bus, the drain is connected to the output bus of the element and the source of the third MOS transistor, the drain and gate 24 26 27 25 which is connected to the second power bus, the addition element and modulo two contains five MOS transistors, the gate of the first of which is connected to the first input bus of the element, the gate and drain of the second MOS transistor and the source of the third MOS transistor, the gate of which is connected to the second the input bus of the element, the source of the first MOS transistor and the gate and drain of the fourth MOS transistor, whose source is connected to the first power bus and the source of the second MOS transistor, the drain of the first MOS transistor is connected to the drain of the third MOS transistor of the resistor, the output bus of the element and the source of the fifth MOS transistor, the gate and drain of which are connected to the second power bus, the 2-2I-2 OR NOT element contains five MOS transistors, the j-gate of which is connected to the j-th input by the element bus, the source of the 1st MOSFET is connected to the first power line, and its drain is connected to the source of the (I + 2} -th MOSFET, the drain of which is connected to the output bus of the element and the source of the fifth MOSFET, the gate and the drain of which is connected to the second power bus, element 4-2I-4 OR NOT contains nine MOS transistors, with creates a K-th of which (K 1,2 ... 8) is connected to the K-th input bus element, a source j-ro MOS transistor is connected to a first power rail, and its drain connected to the source (j. + 4) -th MOSFET, the drain of which is connected to the output bus by the elements of the source of the ninth MOSFET, the gate and source of which are connected to the second power bus. UU23 28 ips U-22 Figure 2 Sha 70