SU1277384A1 - Output signal conditioner - Google Patents

Abstract

The invention relates to electronic switching and computing. It can be used in integrated circuit I / O devices. The purpose of the invention is the extension of functionality - achieved by introducing into the driver the output signal of the second element AND-HE 5 and the comparison device 6, consisting of the element 1-ШИ-И / НЕ 7 and two inverters 8 and 9. The driver also contains trunk element 1, element OR-NOT 2, first element AND-NOT 3, inverter 4, inputs - information 10, gating 11, output bus 12, control bus 13, power bus 14 and common bus 15. Introduction of the comparison device 6 allows monitor the completion of the transfer process through the shaper at different loads at the output of the shaper i and use the signal of the control bus 13 to improve temporal characteristics (information exchange between different blocks of the information processing system. 1 ill. IC with cx 4ib

Description

The invention relates to electronic switching and computing technology and can be used in buffer I / O devices of integrated circuits.

The purpose of the invention is to expand the functionality by introducing a comparator device implemented on the W-I / NES logic elements, comparing the input and output signals and increasing the control signal of coincidence at the end of the operation. The drawing shows a schematic diagram of the device. The device contains a master element 1, an element N1-NOT 2, the first element AND-NO 3, the first inverter 4, the second element AND-NOT 5, the comparison device 6, consisting of the element OR-AND / NOT 7, the second 8 and the third 9 inverters. Information input 10 is connected to the first inputs of the first AND-NOT 3 element and IZH-NOT 2 element, as well as to the second inverter input by the First input of the OR-AND / NOT 7. Element. The input of the driver 11 is connected to the second inputs of the First 3 and the second 5 elements AND-NOT and through the first inverter 4 to the second input of the element OR-NOT 2. The output bus 12 of the forwarder is connected to the second input of the element OR-AND / NOT 7 and through the third the inverter to the third input of the same element SH - AND / NOT, the fourth input of the element OR-AND / is NOT connected to the output of the second inverter 8, and the output - from p The second input is the IS-NE 5 element, the output of which is connected to the control panel 13 of the driver. The main element 1 consists of series-connected complementary VDP transistors and is connected between the power supply 14 and the common bus 15. The drains of MOS transistors are connected to the output bus 12 of the driver, and the gates of p - and p - channel MOS transistors, respectively, with the outputs of the first element AND NOT 3 and element OR NOT 2. The output driver works as follows. Information input 10 receives information (logical 0 or logical 1). At some point in time from the control device to the gate input 11 of the driver

a signal is received that allows information to be output to the output bus 12. At the same time, a logical O is formed at the output of the NAND 3 element and, accordingly, the MOS transistor of the p-type main element 1 is opened, or at the output of the OR-NOT 2 element

Claims (1)

II 4 M and, accordingly, opens the n-type DF transistor. Accordingly, a logic level 1 or a logic level O is formed on the output bus 12. Depending on the capacitive load on the output bus 12, the information output time changes and the corresponding device, including the specified output driver, should track the end of information output. Formed on the output bus 12, the logic level is fed to the corresponding input of the element YUSH-I / NOT 7 and the third inverter 9. At the output of the element OR-I / NOT 7 after the match of the transmitted information from the information input 10 and the information generated on the output bus 12, is a logical 1 signal, which, in the presence of a strobe signal, provides the output of the second element AND-HE 3 and, therefore, on the control bus 13 of the device, the formation of a logical O signal. The appearance of this signal indicates the end of the operation s issuance information for device control strobe signal on the strobe input 11, and thus permits the transition to the next stage of processing. If the signals on the information input 10 of the device and the output bus 12 do not match, the device compares the logical O signal, which, in the presence of a strobe signal, outputs a logical 1 signal on the control bus 13, which indicates that the transient on the output bus 12 is incomplete. Comparison allows you to monitor the completeness of the process of transmitting information through the driver at various loads on the output bus of the device and use the generated control signal shaper tires to improve harak3 teristics time exchange of information between different blocks of information and you numerals systems. An inventive output shaper containing an OR-NOT element, the first AND-NOT element, a first inverter and a main element, consisting of two series-connected NDC transistors of p and n type, whose gates are connected to the outputs of the first element, respectively AND-N and the element ШИИ-НЕ, and the drains of which are connected to the output bus of the device, the first inputs of the element ИШ-НЕ and the first element И-НЕ are connected and connected to the information input of the former, the second input of the first element IS-NOT and the input of the first inverter under Connected to the gate input of the former, the output of the first inverter 84 is connected to the second input of the element SH1I-NOT, characterized in that, in order to expand the functionality of the device, the second element AND-NOT and the comparison device containing the element OR-AND / NOT and the second and third inverters, the first and second inputs of the element OR-AND / NOT, being the first pair of inputs of this element, are connected to the information input and output bus of the device, which in turn are connected via the second and third inverters to the third and fourth inputs of the OR-AND / NOT element, which are the second pair of inputs of this element, the output of the OR-AND / NOT element and the gating input of the device are connected to the inputs of the second NAND element, the output of which is connected to the control driver of the imaging unit.