KR930004717Y1 - High speed cmos dynamic buffer circuit - Google Patents

Abstract

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Description

High Speed CMOS Dynamic Buffer Circuit

1 is a conventional CMOS dynamic buffer circuit.

2 is a CMOS dynamic buffer circuit of the present invention.

3 is an exemplary view of the present invention.

* Explanation of symbols for main parts of the drawings

FET11-FET13: Field effect transistor C11: Capacitor

The present invention relates to a high speed CMOS dynamic buffer circuit, and more particularly, to a high speed CMOS dynamic buffer circuit suitable for an input / output structure of a CMOS integrated circuit requiring high speed input / output.

In the conventional CMOS dynamic buffer circuit, as shown in FIG. 1, the clock perks input terminal CK is commonly connected to the gates of the P-type field effect transistor FET1 and the N-type field effect transistor FET3, and the input is performed. The signal terminal IN is connected to the gate of the N-type field effect transistor FET2, and the field effect transistors FET1-FET3 are connected in series to operate as an inverter, and the source of the field effect transistors FET1 and FET2 is connected. And a drain connection point were respectively connected to the gates of the P-type field effect transistor FET4 and the N-type field effect transistor FET5 connected in series with the power supply terminal Vcc, and operated as an inverter for the output of the preceding stage.

However, such conventional CMOS dynamic buffer circuits have a defect that cannot be used in CMOS integrated circuits requiring high speed input / output.

The present invention is conceived to improve the operation speed of the sea mode dynamic buffer by the action of a capacitor that acts as a charge pump in view of the conventional defects, which will be described in detail with reference to the accompanying drawings.

2 is a high-speed CMOS dynamic buffer circuit diagram of the present invention, as shown in this figure, the clock perks input terminal CK is connected to the gates of the P-type field effect transistors FET11 and FET212, respectively, and the input signal terminal IN Is connected to one terminal of the capacitor (C11) and the gate of the N-type field effect transistor (FET13) through the field effect transistor (FET12), the clock perks input terminal (CK) to the other terminal of the capacitor (C11). In addition, the connection point is configured by connecting the field effect transistors FET11 and FET13 to the output terminal OUT, respectively. The operation and effects of the present invention thus constructed will be described in detail as follows.

When a low potential pulse is applied to the input signal terminal IN and a high potential clock pulse is applied to the clock perks input terminal CK, it is applied to the gate of the P-type field effect transistor FET11 (FET12) to turn off each of them. Accordingly, the clock pulse is not output to the output terminal OUT. When a high potential pulse is applied to the input signal terminal IN and a low potential clock pulse is applied to the clock perks input terminal CK, it is applied to the gate of the P-type field effect transistor FET11 (FET12), and thus the input The high potential pulse applied to the signal terminal IN is applied to the capacitor C11 and charged, and is applied to the gate of the N-type field effect transistor FET13, and at this time, the low potential clock applied to the clock perks input terminal CK. The pulse is output to the output terminal OUT through the P-type field effect transistor FET11. In this state, a high potential clock pulse is applied to the clock perks input terminal CK, which is applied to the gates of the P-type field effect transistors FET11 and FET12 to turn them off. Since the charging voltage of the capacitor C11 is applied to the gate of the FET13, the high potential clock pulse is immediately output to the output terminal OUT through the N-type field effect transistor FET13.

3 is a two-input dynamic oar circuit diagram in which the CMOS dynamic buffer circuit of the present invention is connected in two stages. A low potential clock pulse is applied to the clock perks input terminal CK, and the input signal terminals IN1 (IN2) are shown. When a high potential signal is applied to one or more of the terminals, it is charged in capacitor C11, condensate C21, or both. Therefore, the next high potential clock pulse can be immediately output to the output terminal OUT.

As described in detail above, when the low potential clock pulse is applied, the capacitor is charged to the high potential input path, and the next high potential clock pulse is applied to the output terminal immediately.

Claims (1)

The clock perks input terminal CK is commonly connected to the gates of the P-type field effect transistors FET11 and FET12, the source of the P-type field effect transistor FET11, the other terminal of the capacitor C11, and the N-type. After common connection to the drain of the field effect transistor FET13, the input signal terminal IN is connected to one side terminal of the capacitor C11 and the gate of the N-type field effect transistor FET13 through the P-type field effect transistor FET12. A high speed CMOS dynamic buffer circuit, comprising: a common connection to a drain of the P-type field effect transistor (FET1) and a source of the N-type field effect transistor (FET13) connected to an output terminal (OUT).