RU1774472C - Dinamic d-flip-flop with third output state - Google Patents

Abstract

The invention allows to increase the speed of devices while reducing the required number of MOS transistors and can be used to build output buffer devices in memory circuits, registers, trunk amplifiers. The inventive device contains MOS transistors 1-6, respectively, of the first (p) and second (p) type, bi-directional switch 7, containing two parallel-connected MIS transistors of the first (p) and second (p) type, output stage 8 containing two MOS transistors of the first (p) and second (p) type, the sources of which are connected respectively to the first 9 (power) and second 10 (common) power buses, the drains are connected to the output 11 of stage 8, and the gates are connected respectively to the first 12 and second 13 inputs of the cascade 8. 1 ill. Yo

Description

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The invention relates to pulsed and digital technology and can be used in the construction of universal and specialized digital devices: storage devices, static, quasistatic and dynamic registers, buffer devices of the main exchange, including in SDP integrated circuits.

Known (Shilo VL Popular digital microcircuits. Handbook. - M .: Radio and communications, 1987) various trigger circuits with a third output state (see the indicated source, p. 230, fig., 2.31a - microcircuit K561TP2 and p. 280, Fig. 2.81a as part of microcircuit K564AG1).

The disadvantages of the known circuits are the relatively high complexity, expressed in the required number of equivalent MOS transistors, as well as the relatively low speed due to the use of passive bidirectional keys in the output stage or because of the large number of stages of the output stage control circuit, including additional delay.

There is a known scheme of a dynamic D-trigger with a third output state (Muroga S. System design of super-large integrated circuits: in 2 books, book 1. / Transl. From English - M .: Mir, 1985, p. 259 , Fig. 4.9.19c), consisting of two cascades in series.

A disadvantage of the known circuit is the relatively low speed due to the use of series-connected MOS transistors in the output stage.

Closest to the technical nature of the invention is a circuit of a dynamic D-flip-flop with a third output state (DATA BOOKCOS / MOS B-SERIES DEVICES. 3-Rd IEDITION, 1982, p. 166 HCC / HCF 4034 V and p. 523 HCC / HCF 40104 B), which is part of the register stage circuits. The known circuit contains an output stage, consisting of two MIS transistors of the first and second type, the sources of which are connected respectively to the first and second power buses, the drains are connected to the output of the cascade, and the gates are connected respectively to the first and second inputs of the cascade, a bi-directional key containing two parallel-connected MIS transistors of the first and second type, the sources and drains of which are connected respectively to the information terminals of the key, and the gates are connected respectively by the first and second clock buses, inv rtiruyuschy cascade input and output of which are connected respectively to the output and the first bidirectional switch element inputs and 2I-NO 2 or-NO, whose outputs are connected to first and second inputs of the output stage, and second inputs connected to the gate of the paraphase tires.

A disadvantage of the known circuit is the relatively low speed due to the relatively large number of stages in the control circuit of a powerful output stage, as well as the increased number of required MOS transistors for constructing the circuit.

The purpose of the invention is to improve performance while reducing the required number of MOS transistors.

The goal is achieved due to the fact that in the D-trigger with a third output state, containing an output stage, consisting of two MOS transistors of the first and second type, the sources of which are connected respectively to the first and second power buses, the drains are connected to the output of the cascade , and the gates are connected respectively to the first and second inputs of the cascade, a bi-directional key containing two parallel-connected MOS transistors of the first and second type, the sources and drains of which are connected respectively to the information terminals of the key, are entered the second, third, fourth and fourth, fifth, sixth MOS transistors of the first and second types, respectively, the first and second transistors connected in series between the first power bus and the first input of the output stage, the fourth and fifth transistors connected in series between the second power bus and the second input of the output stage, the third and sixth transistors are connected respectively between the first, second power lines and the first, second inputs of the output stage, the information outputs of the bidirectional switch are connected respectively actually with the first and second inputs of the output stage, and the gates of the transistors of the first and second type of switch are connected respectively to the gates of the sixth and third transistors and connected to the corresponding paraphase control buses, the gates of the first and second transistors are connected respectively to the paraphase clock buses, and the gates of the first and the fourth transistor connected to the input of the trigger circuit, the output of which is connected to the output of the output stage.

No solutions with features are known.

similar distinctive. Together with known features, they exhibit properties unknown previously from other solutions. Thus, the proposed device meets the criterion of significant differences.

The drawing shows a diagram of a D-flip-flop with a third output state, which contains the first 1, second 2, third 3 and fourth 4, fifth 5, sixth b MOS transistors of the first (p) and second (p ) type, bidirectional switch 7, containing two parallel-connected MIS transistors of the first (p) and second (p) type, output stage 8, containing two MIS transistors of the first (p) and second (p) type, the sources of which are connected respectively to the first 9 (power) and second 10 (common) power buses, the drains are connected to the output 11 of stage 8, and the gates are connected s respectively to the first 12 and second

13 of the inputs of cascade 8. Transistors 1,2 are connected in series between bus 9 and input 12, transistors 4,5 are connected in series between bus 10 and input 13, transistors 3,6 are connected respectively between buses 9,10 and inputs 12,13. The information outputs of the key 7 are connected respectively between the inputs 12 and 13 of the cascade 8, the gates of the p- and p-type transistors of the key 7 are connected respectively to the gates of the transistors 6 and 3 and are connected respectively to direct 14 (E) and inverse 15 (E) paraphase buses management. The gates of transistors 5 and 2 are connected respectively to the direct 16 (C) and inerserny 17 (C) clock buses, the gates of transistors 1 and 4 are connected to the information (D) input 18 of the trigger circuit, the output 19 (0) of which is connected to the output 11 of stage 8 .

A D-trigger with a third exit state operates as follows.

Let the potential of the power bus 9 correspond to logical 1, and the common bus 10 to logical O. Then, when applied to the bus

14 and 15 of the levels 1 and O, respectively, open transistors 6 and 3, closing the transistors of the key 7, setting the inputs O and 1, respectively, the levels O and 1, closing the transistors of the output stage 8, and regardless of the signals at the other inputs of the circuit at the circuit output third (high resistance) state. If the opposite levels are set on buses 14 and 15 - O and 1, respectively, then the operation of the circuit depends on the signal levels at the inputs 16.17 and 18 levels. Transistors 6 and 3 are closed, and the transistors of the key 7 are opened, combining the inputs 12 and 13 of stage 8. In this mode, when signals C 1 and C 0 are applied to inputs 16 and 17, transistors 5 and 2 are opened and the signal from input 18 is transmitted to output 19 trigger circuits. This mode can be called the recording-broadcast mode of the signal from input D. When changing the 5 signals on clock 16 and 17 to the opposite (С О, С 1), the trigger circuit enters the dynamic () mode of storing information in the internal nodes of the circuit. In more detail and impudently, the operation of the circuit 10 is shown in the table, where the symbols + and - indicate the on and off state of the transistors of the circuit, respectively. The symbol X defines the third state at the output of the circuit. Symbols and 15 Q reflect the states at the output and inputs of the output stage in the dynamic storage mode.

The proposed D-flip-flop circuit with a third output state allows 0 to obtain a positive effect consisting in an increase in speed in comparison with the prototype circuit. To evaluate the speed of the compared circuits, we will use the linear R-C-model 5 (r-model), based on the summation of the time constants (t) of series-connected cascades. Let the channel resistance of the open transistor be equal to R, and the gate, source or drain capacities equal to C. 0 Then, for the prototype circuit of the summation prototype, the time constant is proportional to the delay of the information input (taking into account the cascade of the signal source inverter) to the output of the control circuit (gate outputs 5 AND-NOT , OR-NOT or inputs 12.13 of cascade 8), will be approximately 18RC (R-4 C + 0.5R 4C + + R 4C + 2R 4C) for four cascades in series.

In the proposed circuit, there is only 0 one cascade, containing in the worst case, with transistors connected in series (1,2, transistors of the key 7 or 4,5, transistors of the key 7). The time constant of this cascade for the worst case does not exceed 5 12RC (2R-5C + 0.5R 4C). Thus, the proposed scheme is more efficient in terms of speed in comparison with the prototype scheme at least 1.5 times (50%).

0 The additional efficiency of the proposed circuit is determined by the smaller number of MOS transistors required for its construction. The proposed solution requires only 10 MOS transistors. whereas the prototype circuit 5 contains at least 14 MOS transistors (counting at least two transistors per inverter and a bi-directional switch and four transistors in circuits 2I-NOT and 2OR-NOT) .. Thus, the additional effect on the number of transistors can reach 40 %

Claims (1)

SUMMARY OF THE INVENTION A dynamic D-flip-flop with a third output state containing an output stage consisting of two MOS transistors of the first and second types, the sources of which are connected to the first and second power buses, the drains are connected to the output of the cascade, and the gates respectively, connected to the first and second inputs of the cascade, an upstream key containing two parallel-connected MIS transistors of the first and second type, the sources and drains of which are connected respectively to the information terminals of the key, and in order to increase speed while reducing the required number of MOS transistors, the first, second, third and fourth, fifth, sixth, MIS transistors of the first and second types, respectively, are introduced, the first, second the transistor is connected in series between the first power bus and the first input of the output stage, the fourth, fifth transistor is connected in series between the second power bus and the second input of the output stage, the third, sixth transistors are connected respectively between the first, second power buses and the first, second inputs of the output stage, the information outputs of the bi-directional key are connected respectively to the first and second inputs of the output stage, and the gates of the transistors of the first and second type keys are connected respectively with the shutters the sixth and third transistors and are connected to the corresponding paraphase control buses, the gates of the first and second transistors are connected respectively to the paraphase clock buses, and the gates of the first and fourth transistors are connected to the inputs of the trigger circuit, the output of which is connected to the output of the output stage.