SU1234952A1 - Flip-flop based on insulated-gate field-effect transistors - Google Patents

Abstract

The invention relates to a pulse technique. It can be used in various electronic devices of automation, telemechanics and computer technology. The purpose of the invention, the extension of functionality, is achieved by introducing in the trigger of a third steady state. To do this, the fifth, sixth, seventh, and eighth MIS transistors (positions 13, 14, 15, and 16, respectively) are additionally introduced into the trigger. The trigger also contains MIS transistors I, 2, 3, and 4, common bus 5, outputs 6 and 9, resistors 7, 10, 17, and 18, power supply bus 8, inputs 11, 2, and 19. In the first steady state, the trigger consumes less energy than avush others, since the values of resistors 17 and 18 are many times greater than the values of resistors 7 and 10. I nl. w y 00 N x O1 th

Description

The invention relates to a pulse technique and can be used in various electronic devices of automation, remote control and computer technology.

The purpose of the invention is to expand the functionality.

The drawing shows an electrical circuit of a trigger on MIS transistors.

The trigger on MOSFETs contains the first 1, second 2, third 3 and fourth 4 A1DG1 transistors, the sources of which are connected to a common nshnaya 5, the drains of the first 1 and second 2 transistors are connected to the first output 6 and connected to bus 8 via the first resistor 7 power, drain the third 3 and fourth 4 transistors connected to the second output 9 and through the second resistor 10 connected to the power supply bus 8, the gates of the first 1 and fourth 4 transistors are connected respectively to the first 11 and second 12 inputs, the sources of the first 13, sixth 14, seventh 15th and eighth 16 transist ores are respectively connected to the common bus 5, the drains of the first 13 and sixth 14 transistors are connected to the gate of the second transistor 2 and through the third resistor 17 are connected to the output 9 and the gate of the eighth transistor 16, the drains of the seventh 15 and eighth transistors 16 3 and through the fourth resistor 18 are connected to the output 6 and the gate of the transistor 13, the gates of the sixth 14 and the seventh 15 transistors are connected to the third input 19.

The trigger on the MOS transistors works as follows.

For example, in the first state, transistors 2 and 3 are closed and at outputs 6 and 9 are high, and at the inputs 11,12 and 19 - low potentials. The high potentials from the outputs 6 and 9, respectively, arrive at the gates of the transistors 13 and 16, which are open, and therefore the potentials of the gates of the transistors 2 and 3 are low, due to which the threeterm is in a steady state. Transistors 1,4,14 and 15 are closed, because their potentials are low.

If the positive impulse 1 pulse arrives at the input 11, the transistor 1 opens at the output 6 and low potentials are set at the gate of the transistor 13. The transistor 13 is closed, and a high potential from output 9 through the resistor 17 enters the gate of transistor 2 and opens it. At the end of the positive pulse at the input 11, the transistor 1 closes, however, the potential 6 remains at the output 6, because the transistor 2 is open, i.e. the trigger switches to the second steady state, in which the transistors 2 and 16 are open, output 6 is low, and output 9 is high notional.

If in the nerve state of the trigger input

12 a positive pulse arrives, then transistor 4 is opened and similarly to the described process due to the symmetry of

the flip-flop switches to the third steady state, in which transistors 3 and

13 are open, and the rest are zakrggy transistors, output 6 is high, and output 9 is low potentials.

If the trigger is in the second steady state and a positive pulse arrives at input 12, then transistor 4 opens, which leads to the establishment of a low potential at output 9 and the gate

transistor 16, which closes. At the gate of transistor 2, a low potential is also set (the gate capacitance is discharged through resistor 17 and open transistor 4} and transistor 2 closes, which leads to high potential at output 6, gate of transistor 13 and at transistor 3 closed), which leads to the opening of the transistors 13 and 3. At the end of the positive pulse at the input 12, the transistor 4 closes and the trigger remains in the third steady state, in which the transistors 3 and 13 are open, and the remaining transistors dips, output 6 is high, and output 9 is low potentials. If the trigger is in the third steady state and a positive pulse arrives at input 11., similarly, the trigger switches to the second steady state due to circuit symmetry. the pulse arrives at input 19, regardless of the previous state of the trigger, transistors 14 and 15 are opened, low potentials are set at the gates of transistors 2 and 3, which causes one of the transistors 1 and 3 to close and Mexico City and the potential opening

the transistors 13 and 16. At the end of the positive pulse at the input 19, the transistors 14 and 15 are closed, and the trigger remains in a steady state nerve, in which the transistors 13 and 16 are open, and all other transistors are closed, at outputs 6 and 9

high potentials.

Thus, by positive impulses (or potentials exceeding the opening voltage of MOS transistors) applied to one of the three inputs 11,12 or 19, the trigger can be switched from one of three stable states irrespective of the usual.

In the first steady state, the trigger consumes much less energy than in the other two, since the values of resistors 17 and 18 are many times sick of the values of resistors 7 and 10.

Claims (1)

Invention Formula Trigger on MOS transistors containing the first, second, third and fourth MOS transistors, whose sources are connected to the bus bar, the drains of the first and second transistors are connected to the first output and connected to the power bus through the first load element with the second output and through the second load element are connected to the power bus, the gates of the first and fourth transistors are connected respectively to the first and second inputs, characterized in that functional widths, the fifth, sixth, seventh and eighth MIS transistors are introduced into it, whose sources are connected to the common bus, the outlets of the fifth and sixth transistors are connected to the gate of the second transistor, and through the third resistor are connected to the second output and gate of the eighth transistor, the drains of the seventh and eighth transistors are connected to the gate of the third transistor, and through the fourth resistor are connected to the first output and the gate of the fifth transistor, the gates of the sixth and seventh transistors are connected to the third input .