KR970051112A - Sink RAM with Dual Output Ports - Google Patents

Sink RAM with Dual Output Ports Download PDF

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Publication number
KR970051112A
KR970051112A KR1019950052607A KR19950052607A KR970051112A KR 970051112 A KR970051112 A KR 970051112A KR 1019950052607 A KR1019950052607 A KR 1019950052607A KR 19950052607 A KR19950052607 A KR 19950052607A KR 970051112 A KR970051112 A KR 970051112A
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KR
South Korea
Prior art keywords
output
port
static
data bus
ram
Prior art date
Application number
KR1019950052607A
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Korean (ko)
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KR0172338B1 (en
Inventor
이중언
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김광호
삼성전자 주식회사
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Priority to KR1019950052607A priority Critical patent/KR0172338B1/en
Publication of KR970051112A publication Critical patent/KR970051112A/en
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Publication of KR0172338B1 publication Critical patent/KR0172338B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

듀얼 출력 포트를 가지는 싱크 램에 관한 것이다.It relates to a sink RAM with dual output ports.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

다이나믹 데이터 버스 및 스태틱 데이터 버스를 공유해서 사용하기 위한 싱크 램을 제공함에 있다.The purpose is to provide a sink RAM for sharing the dynamic data bus and the static data bus.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

듀얼 출력 포트를 가지는 스태틱 싱크 램에 있어서, 스태틱 메모리로부터의 한 쌍의 비트라인과 접속되어 그 비트라인의 미세한 전압차이를 감지하여 증폭하기 위한 제 1수단과, 상기 제 1수단의 출력단과 접속되고, 클럭과 출력인에이블 신호가 입력되는 제 2수단에 의해 제어되고 다이나믹 데이터 버스 포트용 출력신호를 출력하기 위한 제 1출력포트와, 상기 제 1수단의 출력단과 상기 제 1출력포트의 입력단과 공통 접속되고, 서브출력인에이블 신호에 의해 제어되어 스태틱 데이터 버스 포트용 출력신호를 출력하기 위한 제 2출력포트로 이루어지는 것을 특징으로 하는 듀얼 출력 포트를 가지는 것을 요지로 한다.A static sync RAM having a dual output port, comprising: a first means connected to a pair of bit lines from a static memory to sense and amplify minute voltage differences between the bit lines, and an output terminal of the first means; And a first output port controlled by a second means into which a clock and an output enable signal are input, for outputting an output signal for a dynamic data bus port, common with an output end of the first means and an input end of the first output port. It is essential to have a dual output port connected to and controlled by a sub-output enable signal and configured as a second output port for outputting an output signal for the static data bus port.

4. 발명의 중요한 용도4. Important uses of the invention

듀얼 출력 포트를 가지는 싱크 램에 적합하다.Suitable for sink ram with dual output ports.

Description

듀얼 출력 포트를 가지는 싱크 램Sink RAM with Dual Output Ports

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 듀얼 출력 포트를 가지는 싱크 램을 보인 도면.Figure 4 shows a sink RAM with dual output ports in accordance with the present invention.

제5도는 본 발명에 따른 다이나믹 버스를 통한 리이드동작의 타이밍을 보인 도면.5 is a view showing timing of a lead operation through a dynamic bus according to the present invention.

제6도는 본 발명에 따른 다이나믹 버스를 통한 라이드동작의 타이밍을 보인 도면.6 illustrates timing of a ride operation through a dynamic bus according to the present invention.

Claims (4)

듀얼 출력 포트를 가지는 스태틱 싱크 램에 있어서: 스태틱 메모리로 부터의 한 쌍의 비트라인과 접속되어 그 비트라인의 미세한 전압차이를 감지하여 증폭하기 위한 센스 앰프와; 상기 센스 앰프의 출력단과 접속되고, 클럭과 출력인에이블 신호가 입력되는 앤드게이트에 의해 제어되고 다이나믹 데이터 버스 포트용 출력신호를 출력하기 위한 삼상 버퍼와; 상기 센스 앰프의 출력단과 접속되고, 서브 출력인에이블 신호에 의해 제어되어 스태틱 데이터 버스 포트용 출력신호를 출력하기 위한 삼상 버퍼로 이루어지는 것을 특징으로 하는 듀얼 출력 포트를 가지는 스태틱 싱크 램.A static sync RAM having a dual output port, comprising: a sense amplifier connected to a pair of bit lines from a static memory to sense and amplify minute voltage differences between the bit lines; A three-phase buffer connected to an output of the sense amplifier, controlled by an AND gate to which a clock and an output enable signal are input, and outputting an output signal for a dynamic data bus port; And a three-phase buffer connected to an output of the sense amplifier and controlled by a sub-output enable signal to output an output signal for the static data bus port. 제1항에 있어서; 상기 삼상 버퍼는 메모리 내부에서 발생되는 상기 클럭과 상기 출력인에이블 신호가 논리곱되어 상기 클럭이 "하이"레벨이 될 경우에만 활성화되는 것을 특징으로 하는 듀얼 출력 포트를 가지는 스태틱 싱크 램.The method of claim 1; And the three-phase buffer is activated only when the clock generated in the memory is multiplied by the output enable signal and the clock becomes a "high" level. 제1항에 있어서; 상기 삼상 버퍼는 상기 앤드게이트에 의해 제어되는 것을 특징으로 하는 듀얼 출력 포트를 가지는 스태틱 싱크 램.The method of claim 1; Wherein said three-phase buffer is controlled by said AND gate. 듀얼 출력 포트를 가지는 스태틱 싱크 램에 있어서: 스태틱 메모리로 부터의 한 쌍의 비트라인과 접속되어 그 비트라인의 미세한 전압차이를 감지하여 증폭하기 위한 제 1수단과; 상기 제 1수단의 출력단과 접속되고, 클럭과 출력인에이블 신호가 입력되는 제 2수단에 의해 제어되고 다이나믹 데이터 버스 포트용 출력 신호를 출력하기 위한 제 1출력포트와; 상기 제 1수단의 출력단과 상기 제 1출력포트의 입력단과 공통 접속되고, 서브출력인에이블 신호에 의해 제어되어 스태틱 데이터 버스 포트용 출력신호를 출력하기 위한 제 2출력포트로 이루어지는 것을 특징으로 하는 듀얼 출력 포트를 가지는 스태틱 싱크 램.A static sync RAM having a dual output port, comprising: first means connected to a pair of bit lines from a static memory to sense and amplify minute voltage differences between the bit lines; A first output port connected to an output end of said first means, controlled by second means for inputting a clock and an output enable signal and for outputting an output signal for a dynamic data bus port; And a second output port connected in common with an output terminal of the first means and an input terminal of the first output port and controlled by a sub-output enable signal to output an output signal for the static data bus port. Static sync ram with output port. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052607A 1995-12-20 1995-12-20 Synchronous random access memory having dual output port KR0172338B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950052607A KR0172338B1 (en) 1995-12-20 1995-12-20 Synchronous random access memory having dual output port

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KR970051112A true KR970051112A (en) 1997-07-29
KR0172338B1 KR0172338B1 (en) 1999-03-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100485691B1 (en) * 2002-11-20 2005-04-27 (주)씨앤에스 테크놀로지 Conflict prevention method of synchronous data bus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100485691B1 (en) * 2002-11-20 2005-04-27 (주)씨앤에스 테크놀로지 Conflict prevention method of synchronous data bus

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Publication number Publication date
KR0172338B1 (en) 1999-03-30

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