KR970012741A

KR970012741A - Row Address Buffers in Semiconductor Memory Devices

Info

Publication number: KR970012741A
Application number: KR1019950026283A
Authority: KR
Inventors: 최종현
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-08-24
Filing date: 1995-08-24
Publication date: 1997-03-29

Abstract

본 발명은 반도체 메모리 장치의 행 어드레스 버퍼를 공개한다. 그 회로는 제1어드레스 입력신호를 제1어드레스 입력제어신호에 응답하여 출력하기 위한 제1어드레스 입력수단, 제2어드레스 입력신호를 제2어드레스 입력제어신호에 응답하여 출력하기 위한 제2어드레스 입력수단, 및 제어신호에 응답하여 상기 제1 및 제2어드레스 입력수단으로부터의 출력되는 신호를 행 어드레스 신호로 출력하되, 상기 행 어드레스 신호를 정상 리드/라이트 모드 동작시에 리플레쉬 모드 동작시보다 먼저 출력하기 위한 어드레스 출력수단으로 구성되어 있다. 따라서, 정상 모드/라이트 모드 동작과 리플레쉬 모드 동작시에 제어신호의 인에이블시점을 달리 제어함으로서 동작속도를 향상시킬 수 있다.The present invention discloses a row address buffer of a semiconductor memory device. The circuit includes first address input means for outputting a first address input signal in response to a first address input control signal, and second address input means for outputting a second address input signal in response to a second address input control signal. And output a signal output from the first and second address input means as a row address signal in response to a control signal, wherein the row address signal is output before the refresh mode operation in the normal read / write mode operation. It is composed of an address output means for doing this. Therefore, the operation speed can be improved by controlling the enable time of the control signal differently during the normal mode / right mode operation and the refresh mode operation.

Description

Row Address Buffers in Semiconductor Memory Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 반도체 메모리 장치의 행 어드레스 버퍼의 회로도이다.3 is a circuit diagram of a row address buffer of the semiconductor memory device of the present invention.

Claims

First address input means for outputting a first address input signal in response to the first address input control signal; Second address input means for outputting a second address input signal in response to a second address input control signal; And outputting a signal output from the first and second address input means as a row address signal in response to a control signal, wherein the row address signal is output before the refresh mode operation in the normal read / write mode operation. A row address buffer of a semiconductor memory device, comprising: address output means.

The row address buffer of claim 1, wherein the control signal is output in the normal mode / write mode operation in advance of the additive refresh mode operation.

The row address buffer of claim 1, wherein the second address control signal is activated to output the second address input signal as the address output signal when the first address control signal is deactivated.

2. The circuit of claim 1, wherein the circuit for generating the control signal of the address output means comprises: a delay circuit for outputting a delay signal by inputting a signal PRD; A first and gate having two inputs of the signal PRD and the refresh mode CBRB; An inverter for inverting the CBRB; A second and gate having two inputs of a delay signal of the delay circuit and an output signal of the inverter; And an or gate configured to output the control signal using the output signals of the first and second end gates as two inputs.

※ Note: The disclosure is based on the initial application.