KR970019061A - Data output buffer - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer of a semiconductor memory device, in which two pull-up / pull-down driver stages are output in parallel to output data to an output stage. And the other one is to operate only for a certain time, thereby improving the operation speed when outputting data continuously, and also has the effect of reducing noise.

Description

Data output buffer

Since this is an open matter, no full text was included.

1 is a circuit diagram of a data output buffer according to a first embodiment of the present invention;

2 is a circuit diagram of a data output buffer according to a second embodiment of the present invention.

Claims (10)

A data output buffer in which an output terminal of a semiconductor memory device maintains a high-impedance state, the data output buffer comprising: first pull-up driver means for supplying a power potential to the output terminal when the input signal has a first logic, and the input signal is first A first pull-down driver means for supplying a ground potential to the output terminal when having two logics, and a first edge for detecting an edge signal having a predetermined period width by inputting an inverted signal of an input signal of the first logic; Detection means, second edge detection means for detecting an edge signal having a predetermined period width by inputting an inverted signal of the input signal of the second logic, and only for a time corresponding to an edge signal of the first edge detection means; Second pull-up driver means for supplying a power potential to the output terminal and the output terminal only for a period corresponding to an edge signal of the second edge detection means. Data output buffer comprising: a driver means for down-second pool for supplying the paper potential. 2. The data output buffer of claim 1, wherein said first logic is low and said second logic is high. 2. The data output buffer as recited in claim 1, wherein said first and second pull-up driver means are PMOS. 2. The data output buffer as recited in claim 1, wherein said first and second pull-down driver means are NMOS. 2. The apparatus of claim 1, wherein the first edge detection means and the second edge detection means comprise delay means for delaying an inverted signal of the input signal of the first or second logic for a predetermined time, and the first or second logic. And a logic gate for outputting a logically calculated value by inputting an inverted signal of the input signal and an output signal of the delay means. 6. The data output buffer as claimed in claim 5, wherein said delay means comprises an odd number of inverters. 6. The data output buffer as claimed in claim 5, wherein the logic gate comprises a NAND or NOR gate. 2. The apparatus of claim 1, wherein the first edge detection means and the second edge detection means comprise delay means for delaying an inverted signal of the input signal of the first or second logic for a predetermined period of time, and an output from the delay means. A first logic gate for outputting a logic operation value by inputting a signal and a control signal input from the outside, an inversion signal of the input signal of the first or second logic and an output signal of the first logic gate as inputs And a second logic gate for outputting a logic operation value. 9. The data output buffer according to claim 8, wherein the delay means comprises an even number of inverters. 10. The data output buffer of claim 8, wherein the first and second logic gates are NAND or NOR gates. ※ Note: The disclosure is based on the initial application.