KR970019061A - Data output buffer - Google Patents

Data output buffer Download PDF

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KR970019061A
KR970019061A KR1019950031607A KR19950031607A KR970019061A KR 970019061 A KR970019061 A KR 970019061A KR 1019950031607 A KR1019950031607 A KR 1019950031607A KR 19950031607 A KR19950031607 A KR 19950031607A KR 970019061 A KR970019061 A KR 970019061A
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logic
signal
data output
output buffer
detection means
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이재진
김정필
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김주용
현대전자산업 주식회사
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Abstract

본 발명은 반도체 기억소자의 데이타 출력버퍼에 관한 것으로, 출력 단에 풀-업/풀-다운 드라이버단을 병렬로 각각 2개씩 구현하여 출력단으로 데이타를 출력할때 상기 2개의 드라이버중 하나는 항상 동작하고 나머지 하나는 일정시간동안에만 동작되도록 함으로써, 연속적으로 데이타를 출력시 동작속도를 향상시켰고, 또한 노이즈를 감소시키는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer of a semiconductor memory device, in which two pull-up / pull-down driver stages are output in parallel to output data to an output stage. And the other one is to operate only for a certain time, thereby improving the operation speed when outputting data continuously, and also has the effect of reducing noise.

Description

데이타 출력버퍼Data output buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명의 제1 실시예에 따른 데이타 출력버퍼의 회로도,1 is a circuit diagram of a data output buffer according to a first embodiment of the present invention;

제 2 도는 본 발명의 제2 실시예에 따른 데이타 출력버퍼의 회로도.2 is a circuit diagram of a data output buffer according to a second embodiment of the present invention.

Claims (10)

반도체 기억장치의 출력단자가 하이-임피던스 상태를 유지하는 데이타 출력버퍼에 있어서, 입력신호가 제1논리를 가질때 상기 출력단자로 전원전위를 공급하기 위한 제1 풀-업 드라이버 수단과, 입력신호가 제2 논리를 가질때 상기 출력단자로 접지전위를 공급하기 위한 제1 풀-다운 드라이버 수단과, 상기 제1 논리의 입력신호의 반전신호를 입력으로 하여 일정기간 폭의 에지신호를 검출하기 위한 제1 에지검출수단과, 상기 제2 논리의 입력신호의 반전신호를 입력으로 하여 일정기간 폭의 에지신호를 검출하기 위한 제2 에지검출수단과, 상기 제1 에지 검출수단의 에지신호에 해당하는 시간동안에만 상기 출력단자로 전원전위를 공급하기 위한 제2 풀-업 드라이버 수단과, 상기 제2 에지검출수단의 에지신호에 해당하는 기간동안에만 상기 출력단자로 접지전위를 공급하기 위한 제2 풀-다운 드라이버 수단을 구비하는 것을 특징으로 하는 데이타 출력버퍼.A data output buffer in which an output terminal of a semiconductor memory device maintains a high-impedance state, the data output buffer comprising: first pull-up driver means for supplying a power potential to the output terminal when the input signal has a first logic, and the input signal is first A first pull-down driver means for supplying a ground potential to the output terminal when having two logics, and a first edge for detecting an edge signal having a predetermined period width by inputting an inverted signal of an input signal of the first logic; Detection means, second edge detection means for detecting an edge signal having a predetermined period width by inputting an inverted signal of the input signal of the second logic, and only for a time corresponding to an edge signal of the first edge detection means; Second pull-up driver means for supplying a power potential to the output terminal and the output terminal only for a period corresponding to an edge signal of the second edge detection means. Data output buffer comprising: a driver means for down-second pool for supplying the paper potential. 제 1 항에 있어서, 상기 제1 논리는 로우이고, 상기 제2 논리는 하이인 것을 특징으로 하는 데이타 출력버퍼.2. The data output buffer of claim 1, wherein said first logic is low and said second logic is high. 제 1 항에 있어서, 상기 제1 및 제2 풀-업 드라이버 수단은 PMOS인 것을 특징으로 하는 데이타 출력버퍼.2. The data output buffer as recited in claim 1, wherein said first and second pull-up driver means are PMOS. 제 1 항에 있어서, 상기 제1 및 제2 풀-다운 드라이버 수단은 NMOS인 것을 특징으로 하는 데이타 출력버퍼.2. The data output buffer as recited in claim 1, wherein said first and second pull-down driver means are NMOS. 제 1 항에 있어서, 상기 제1 에지검출수단 및 제2 에지검출수단은, 상기 제1 또는 제2 논리의 입력신호의 반전신호를 일정시간동안 지연시키는 지연수단과, 상기 제1 또는 제2 논리의 입력신호의 반전신호 및 지연수단의 출력신호를 입력으로 하여 논리연산한 값을 출력하는 논리게이트로 구성된 것을 특징으로 하는 데이타 출력버퍼.2. The apparatus of claim 1, wherein the first edge detection means and the second edge detection means comprise delay means for delaying an inverted signal of the input signal of the first or second logic for a predetermined time, and the first or second logic. And a logic gate for outputting a logically calculated value by inputting an inverted signal of the input signal and an output signal of the delay means. 제 5 항에 있어서, 상기 지연수단은 홀수 개의 인버터로 구성된 것을 특징으로 하는 데이타 출력버퍼.6. The data output buffer as claimed in claim 5, wherein said delay means comprises an odd number of inverters. 제 5 항에 있어서, 상기 논리게이트는 NAND 또는 NOR게이트로 구성된 것을 특징으로 하는 데이타 출력버퍼.6. The data output buffer as claimed in claim 5, wherein the logic gate comprises a NAND or NOR gate. 제 1 항에 있어서, 상기 제1 에지검출수단 및 제2 에지검출수단은, 상기 제1 또는 제2 논리의 입력신호의 반전신호를 일정기간동안 지연시키는 지연수단과, 상기 지연수단으로 부터의 출력신호 및 외부에서 입력되는 제어신호를 입력으로 하여 논리연산한 값을 출력하는 제1 논리게이트와, 상기 제1 또는 제2 논리의 입력신호의 반전신호 및 제1 논리게이트의 출력신호를 입력으로 하여 논리연산한 값을 출력하는 제2 논리 게이트로 구성된 것을 특징으로 하는 데이타 출력버퍼.2. The apparatus of claim 1, wherein the first edge detection means and the second edge detection means comprise delay means for delaying an inverted signal of the input signal of the first or second logic for a predetermined period of time, and an output from the delay means. A first logic gate for outputting a logic operation value by inputting a signal and a control signal input from the outside, an inversion signal of the input signal of the first or second logic and an output signal of the first logic gate as inputs And a second logic gate for outputting a logic operation value. 제 8 항에 있어서, 상기 지연수단은 짝수 개의 인버터로 구성된 것을 특징으로 하는 데이타 출력버퍼.9. The data output buffer according to claim 8, wherein the delay means comprises an even number of inverters. 제 8 항에 있어서, 상기 제1 및 제2 논리게이트는 NAND 또는 NOR게이트인 것을 특징으로 하는 데이타 출력버퍼.10. The data output buffer of claim 8, wherein the first and second logic gates are NAND or NOR gates. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950031607A 1995-09-25 1995-09-25 Data output buffer Ceased KR970019061A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100254317B1 (en) * 1997-04-30 2000-09-01 윤종용 Operation cycle adaptive data output buffer
KR100452635B1 (en) * 1997-12-30 2004-12-17 주식회사 하이닉스반도체 Edge detector
KR100622762B1 (en) * 1999-06-29 2006-09-12 주식회사 하이닉스반도체 Data output buffer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100254317B1 (en) * 1997-04-30 2000-09-01 윤종용 Operation cycle adaptive data output buffer
KR100452635B1 (en) * 1997-12-30 2004-12-17 주식회사 하이닉스반도체 Edge detector
KR100622762B1 (en) * 1999-06-29 2006-09-12 주식회사 하이닉스반도체 Data output buffer

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