KR100452635B1 - Edge detector for detecting change time point of input signal by logic combination of input signal, inversed signal, and delay signal - Google Patents

Abstract

PURPOSE: An edge detector is provided to reduce the size of the edge detector by detecting a change point of an input signal through the logic combination of the input signal, an inversed signal of the input signal, and a delay signal of the input signal. CONSTITUTION: An edge detector comprises a time delay unit(11) for delaying an input signal(ADD) for a predetermined time; an inverter(12) for inversing the input signal; and a logic combination unit(13) for taking, as an input, the input signal, an output signal from the time delay unit, and an output signal from the inverter, detecting a change point of the input signal, and outputting a result signal. The logic combination unit includes a first input terminal(a11) for receiving the input signal; a second input terminal(b11) for receiving the output signal from the time delay unit; a third input terminal(c11) for receiving the output signal from the inverter; a first transistor(Q1) connected between the first input terminal and an output terminal(OUT), wherein the first transistor has a gate connected to the second input terminal; a fourth transistor(Q4) connected between the third input terminal and the output terminal, wherein the fourth transistor has a gate connected to the second input terminal; and a second transistor(Q2) and a third transistor(Q3) connected in parallel between the second input terminal and the output terminal, wherein the second and third transistors have gates connected to the first input terminal and the third input terminal, respectively.

Description

Edge detector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an edge detector, and more particularly, to an edge detector capable of detecting a start portion and an end portion, that is, an edge, of a pulse signal required for operation of a semiconductor device.

In general, the edge detector detects an inversion timing of an input pulse signal and generates and outputs a signal having a desired size.

As shown in FIG. 1, the conventional edge detector includes a first detector 1 for detecting a time point at which the input signal ADD changes from high to low, and the input signal ADD at low. The start and end portions of the signal ADD are detected using the second detector 2 and the signals generated from the first and second detectors 1 and 2 for detecting the time point at which the signal is changed to high, and a new output is performed. It consists of a logic combination section 3 for generating a signal ADT.

However, the conventional edge detector configured as described above includes a first detector 1 for detecting a time point at which the input signal ADD changes from high to low, and a time point for detecting a time point at which the input signal ADD changes from low to high. Since the circuit is made of the second detection unit 2, the size of the circuit is large, and the area occupied by the edge detector on the chip is large because it is implemented by a large number of devices. In addition, the power consumption of driving many devices is not small.

Accordingly, the present invention is an edge detector that can solve the above-mentioned disadvantages by logically combining an input signal, a signal in which the input signal is inverted, and a signal in which the input signal is delayed by a predetermined time. The purpose is to provide.

The present invention for achieving the above object is a time delay unit for delaying the input signal for a predetermined time, an inverter for inverting the input signal, the input signal, the output signal of the time delay unit and the output signal of the inverter And a logic combiner for detecting a change point of the input signal and outputting a result signal, wherein the logic combiner comprises a first input terminal receiving the input signal and an output signal of the time delay unit. A second input terminal receiving an input, a third input terminal receiving an output signal of the inverter, a first transistor connected between the first input terminal and an output terminal and having a gate connected to the second input terminal, A fourth transistor connected between a third input terminal and an output terminal and having a gate connected to the second input terminal; Connected in parallel between the output terminal and an output terminal, and is characterized in that the gate is composed of the first input terminal and second and third transistors respectively connected to the third input terminal.

1 is a circuit diagram for explaining a conventional edge detector.

2 is a circuit diagram for explaining a first embodiment of the present invention.

3 is a timing diagram for explaining the present invention.

4 is a circuit diagram for explaining a second embodiment of the present invention.

5 is a circuit diagram for explaining a third embodiment of the present invention.

6 is a graph for explaining the operating characteristics of the edge detector according to the present invention.

<Explanation of symbols for main parts of the drawing

1: first detection unit 2: second detection unit

3, 13, 23, and 33: logic combination

11, 21, and 31: time delay

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a circuit diagram for explaining a first embodiment of the present invention.

The edge detector according to the first embodiment of the present invention includes a time delay unit 11 for delaying the input of the signal ADD for a predetermined time, an inverter 12 for inverting the signal ADD, and the signal ADD. ), A logic of detecting a change point of the signal ADD and outputting a result signal OUT using the output signal ADD1 of the time delay unit 11 and the output signal ADDb of the inverter 12. Combination section 13 is made. In addition, the logic combining unit 13 receives the signal ADD through a first input terminal a11 and output signal ADD1 of the time delay unit 11 through a second input terminal b11. Is inputted, and is configured to receive an output signal ADDb of the inverter 12 through a third input terminal c11, wherein a gate is formed between the first input terminal a11 and the output terminal OUT. A fourth transistor Q1 connected to an input terminal b11 is connected, and a gate is connected to the second input terminal b11 between the third input terminal c11 and the output terminal OUT. Q4) is connected, and a second and third transistor having a gate connected to the first input terminal a11 and the third input terminal c11 between the second input terminal b11 and the output terminal OUT, respectively. (Q2 and Q3) are connected in parallel. In this case, the first and second transistors Q1 and Q2 use PMOS transistors, and the third and fourth transistors Q3 and Q4 use NMOS transistors. Next, the operation of the edge detector will be described with reference to FIG. 3.

First, when the signal ADD is input in the low state as in the period T1 of FIG. 3, the first input terminal a11 of the logic combination unit 13 maintains the low state and the second input. The terminal b11 also maintains a low state because the output signal ADD1 of the time delay unit 11 is not output for a predetermined time. The third input terminal c11 maintains a high state. Therefore, the first, second and third transistors Q1, Q2 and Q3 of the logic combination unit 13 are turned on and the fourth transistor Q4 is turned off. The low level signal is output to the output terminal OUT.

Second, when the signal ADD changes from low to high as in the period T2 of FIG. 3, the first input terminal a11 of the logic combination unit 13 maintains a high state, and the second The input terminal b11 maintains the low state because the signal ADD1 delayed by the time delay unit 11 is output in the low state. The third input terminal c11 also maintains a low state. Therefore, the first transistor Q1 of the logic combination unit 13 is turned on and the second, third and fourth transistors Q2, Q3 and Q4 are turned off so that the output terminal OUT is high. The status signal is output.

Third, when the signal ADD remains high as in the period T3 of FIG. 3, the first input terminal a11 of the logic combination unit 13 maintains a high state and the second input. The terminal b11 also maintains a high state because the signal ADD1 delayed by the time delay unit 11 is output in a high state. The third input terminal c11 maintains a low state. Therefore, the first, second and third transistors Q1, Q2 and Q3 of the logic combination unit 13 are turned off and the fourth transistor Q4 is turned on so that the output terminal OUT is low. The status signal is output.

Fourth, when the signal ADD changes from high to low as in the period T4 of FIG. 3, the first input terminal a11 of the logic combination unit 13 maintains a low state, and the second The input terminal b11 maintains a high state because the signal ADD1 delayed by the time delay unit 11 is output in a high state. The third input terminal c11 also maintains a high state. Therefore, the first transistor Q1 of the logic combination unit 13 is turned off and the second, third and fourth transistors Q2, Q3 and Q4 are turned on so that the output terminal OUT is turned on. A high state signal is output.

That is, when the signals ADD and ADD1 input through the first input terminal a11 and the second input terminal b11 maintain the same state, a low state signal is output through the output terminal OUT. When the signals ADD and ADD1 input through the first input terminal a11 and the second input terminal b11 maintain different states, a signal having a high state is output through the output terminal OUT. .

4 is a circuit diagram for explaining a second embodiment of the present invention.

The edge detector according to the second embodiment of the present invention delays the input of the signal ADD for a predetermined time and outputs a time delay unit for outputting the first and second output signals ADD1 and ADD1b having opposite phases. 21) the change point of the signal ADD is detected by using the signal ADD and the first and second output signals ADD1 and ADD1b of the time delay unit 21, and the resultant signal OUT is output. Consisting of a logical combination section 23. In addition, the logic combiner 23 receives the first output signal ADD1 of the time delay unit 21 through a first input terminal a21 and the signal (B) through a second input terminal b21. ADD), and is configured to receive a second output signal ADD1b of the time delay unit 21 through a third input terminal c21, wherein the first input terminal a21 and the output terminal OUT. The first transistor Q11 having a gate connected to the second input terminal b21 is connected therebetween, and a gate is connected to the second input terminal b21 between the third input terminal c11 and the output terminal OUT. The connected fourth transistor Q14 is connected, and a gate is connected between the first input terminal a21 and the third input terminal c21, respectively, between the second input terminal b11 and the output terminal OUT. The second and third transistors Q12 and Q13 are connected in parallel. In this case, the first and second transistors Q1 and Q2 use PMOS transistors, and the third and fourth transistors Q3 and Q4 use NMOS transistors. The operation of the edge detector will now be described with reference to FIG. 3 again.

First, when the signal ADD is input in the low state as in the time T1 section of FIG. 3, the first input terminal a21 of the logic combiner 23 is the first of the time delay unit 21. Since the output signal ADD1 is not output for a predetermined time, the output signal ADD1 is kept low, and the second input terminal b21 is also kept low. The third input terminal c21 maintains a high state because the second output signal ADD1b of the time delay unit 21 is output in a high state. Therefore, the first, second and third transistors Q1, Q2 and Q3 of the logic combination section 23 are turned on and the fourth transistor Q4 is turned off so that the output terminal OUT is low. The status signal is output.

Second, when the signal ADD changes from low to high as in the period of time T2 of FIG. 3, the first input terminal a21 of the logic combiner 23 is formed of the time delay unit 21. Since the first output signal ADD1 is output in the low state, the low state is maintained, and the second input terminal b21 maintains the high state. The third input terminal c21 also maintains a high state because the second output signal ADD1b of the time delay unit 21 is output in a high state. Therefore, the second, third and fourth transistors Q2, Q3 and Q4 of the logic combination section 23 are turned on and the first transistor Q1 is turned off so that the output terminal OUT is high. The status signal is output.

Third, when the signal ADD remains high as in the period T3 of FIG. 3, the first input terminal a21 of the logic combiner 23 is the first of the time delay unit 21. Since the output signal ADD1 is output in the high state, the state is maintained high, and the second input terminal b21 also maintains the high state. The third input terminal c21 maintains a low state because the second output signal ADD1b of the time delay unit 21 is output in a low state. Therefore, the first, second and third transistors Q1, Q2 and Q3 of the logic combination section 23 are turned off and the fourth transistor Q4 is turned on so that the output terminal OUT is low. The status signal is output.

Fourth, when the signal ADD is changed from high to low, as in the period T4 of FIG. 3, the first input terminal a21 of the logic combiner 23 is formed by the time delay unit 21. Since the first output signal ADD1 is output in a high state, it is maintained in a high state, and the second input terminal b21 is maintained in a low state. The third input terminal c21 also maintains a low state because the second output signal ADD1b of the time delay unit 21 is output in a low state. Therefore, the second, third and fourth transistors Q2, Q3 and Q4 of the logic combination section 23 are turned off and the first transistor Q1 is turned on so that the output terminal OUT is high. The status signal is output.

5 is a circuit diagram for explaining a third embodiment of the present invention.

The edge detector according to the third embodiment of the present invention includes a time delay unit 31 for delaying the input of the signal ADD for a predetermined time and an output signal ADD1 of the signal ADD and the time delay unit 31. It is composed of a logic combination unit 33 for detecting the time of change of the signal ADD by using a) and outputs the resultant signal (OUT). In this case, the logic combining unit 33 may be configured using an exclusive OR gate EXOR. The operation of the edge detector will now be described with reference to FIG. 3 again.

First, when the signal ADD is input in the low state as in the period T1 of FIG. 3, the output signal ADD1 of the time delay unit 31 is not output for a predetermined time, and thus the logic combination unit 33 is used. A low state signal is output to the output terminal OUT of the output terminal OUT.

Second, when the signal ADD is changed from low to high as in the time period T2 of FIG. 3, the output signal ADD1 of the time delay unit 31 is outputted in the low state. A signal in a high state is output to the output terminal OUT of 33).

Third, when the signal ADD remains high, as in the period T3 of FIG. 3, the output signal ADD1 of the time delay unit 31 is outputted in a high state. A low state signal is output to the output terminal OUT of the output terminal OUT.

Fourth, when the signal ADD is changed from high to low as in the period T4 of FIG. 3, the output signal ADD1 of the time delay unit 31 is outputted in the high state so that the logic combination unit ( A signal in a high state is output to the output terminal OUT of 33).

For reference, FIG. 6 is a graph illustrating an operation characteristic of an edge detector according to the present invention, in which line A is a voltage waveform of a signal ADD input to the edge detector, and line B is output from the edge detector. The voltage waveform of the signal OUT is shown. As can be seen from the figure it can be seen that the use of the present invention can quickly detect a change in the pulse signal.

As described above, according to the present invention, an edge detector can be easily implemented by logically combining an input signal, a signal in which the input signal is inverted, and a signal in which the input signal is delayed by a predetermined time. Can be. Therefore, the area occupied by the edge detector on the chip can be minimized, and since only a small number of devices can be driven, the power consumption of the devices can be effectively reduced.

Claims (3)

For edge detectors, A time delay unit for delaying the input signal for a predetermined time; An inverter for inverting the input signal; And an logic combination unit configured to receive the input signal, the output signal of the time delay unit, and the output signal of the inverter, and detect a change point of the input signal and output a result signal. The display apparatus of claim 1, wherein the logic combination unit comprises: a first input terminal configured to receive the input signal; A second input terminal receiving the output signal of the time delay unit; A third input terminal configured to receive an output signal of the inverter; A first transistor connected between the first input terminal and the output terminal and whose gate is connected to the second input terminal; A fourth transistor connected between the third input terminal and the output terminal and whose gate is connected to the second input terminal; And the second and third transistors connected in parallel between the second input terminal and the output terminal and whose gates are connected to the first input terminal and the third input terminal, respectively. The edge detector of claim 1, wherein the first and second transistors are PMOS transistors, and the third and fourth transistors are NMOS transistors.

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