KR950022084A - Pulse Edge Detection Circuit - Google Patents

Pulse Edge Detection Circuit Download PDF

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Publication number
KR950022084A
KR950022084A KR1019930031022A KR930031022A KR950022084A KR 950022084 A KR950022084 A KR 950022084A KR 1019930031022 A KR1019930031022 A KR 1019930031022A KR 930031022 A KR930031022 A KR 930031022A KR 950022084 A KR950022084 A KR 950022084A
Authority
KR
South Korea
Prior art keywords
detection circuit
edge detection
pulse
integrator
edge
Prior art date
Application number
KR1019930031022A
Other languages
Korean (ko)
Inventor
김정세
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930031022A priority Critical patent/KR950022084A/en
Publication of KR950022084A publication Critical patent/KR950022084A/en

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  • Manipulation Of Pulses (AREA)

Abstract

본 발명은 입력펄스의 상승에지와 하강에지를 검출하는 펄스에지검출회로에 관한 것으로, 입력펄스신호를 적분하는 적분기와 적분기의 출력을 입력하여 지연시키는 지연기와 지연된 신호와 입력신호의 위상을 비교하는 위상비교기를 구비하여 입력펄스신호의 상승에지와 하강에지를 검출하는 것을 특징으로 한다.The present invention relates to a pulse edge detection circuit for detecting rising edges and falling edges of an input pulse. A phase comparator is provided to detect the rising edge and the falling edge of the input pulse signal.

Description

펄스에지 검출회로Pulse Edge Detection Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 의한 펄스에지 검출회로를 도시한 회로도이다.3 is a circuit diagram showing a pulse edge detection circuit according to the present invention.

Claims (2)

입력펄스의 상승에지와 하강에지를 검출하는 펄스 에지검출회로에 있어서, 상기 입력펄스신호를 적분하는 적분기; 상기 적분기의 출력을 입력하여 지연시키는 지연기; 상기 지연된 신호와 상기 입력신호의 위상을 비교하는 위상비교기를 구비하여 상기 입력펄스신호의 상승에지와 하강에지를 검출하는 것을 특징으로 하는 펄스에지 검출회로.CLAIMS 1. A pulse edge detection circuit for detecting a rising edge and a falling edge of an input pulse, comprising: an integrator for integrating the input pulse signal; A delayer for inputting and delaying the output of the integrator; And a phase comparator for comparing a phase of the delayed signal and the input signal to detect rising and falling edges of the input pulse signal. 제1항에 있어서, 상기 지연기는 상기 적분기의 출력을 입력하여 구형파를 발생하는 슈미트트리거와, 상기 슈미트트리거의 출력을 반전하는 인버터를 구비한 것을 특징으로 하는 펄스에지 검출회로.2. The pulse edge detection circuit according to claim 1, wherein the delay unit includes a schmitt trigger for inputting an output of the integrator to generate a square wave, and an inverter for inverting the output of the schmitt trigger. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930031022A 1993-12-29 1993-12-29 Pulse Edge Detection Circuit KR950022084A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930031022A KR950022084A (en) 1993-12-29 1993-12-29 Pulse Edge Detection Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930031022A KR950022084A (en) 1993-12-29 1993-12-29 Pulse Edge Detection Circuit

Publications (1)

Publication Number Publication Date
KR950022084A true KR950022084A (en) 1995-07-26

Family

ID=66853279

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930031022A KR950022084A (en) 1993-12-29 1993-12-29 Pulse Edge Detection Circuit

Country Status (1)

Country Link
KR (1) KR950022084A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100452635B1 (en) * 1997-12-30 2004-12-17 주식회사 하이닉스반도체 Edge detector for detecting change time point of input signal by logic combination of input signal, inversed signal, and delay signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100452635B1 (en) * 1997-12-30 2004-12-17 주식회사 하이닉스반도체 Edge detector for detecting change time point of input signal by logic combination of input signal, inversed signal, and delay signal

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