KR100245272B1 - A circuit of detecting address transition of semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device, and more particularly, to an address transition detection circuit of a semiconductor memory device which detects a transition of external addresses and outputs a pulse signal having a predetermined period using the same. And a short pulse generator and a word line tracking pulse generator. The short pulse generator according to the present invention includes a short pulse generator and a short circuit generator. A NAND gate having a first input, a second inverter, a resistor, and a second input terminal for receiving the output signal through the third and fourth inverters, and between the connection point of the resistor and the third inverter and ground. A PMOS transistor having a connected source and a drain connected to a connection point of the resistor and the third inverter According to this circuit configuration, the short pulse generator generates a short pulse signal always having a constant pulse width regardless of the pulse width of the signal output from the summator.

Description

(A circuit of detecting address transition of semiconductor device)

The present invention relates to a semiconductor memory device, and more particularly, to an address transition detection circuit of a semiconductor memory device which detects a transition of external addresses and outputs a pulse signal having a predetermined period using the same.

In an asynchronous semiconductor memory device, an address transition detector circuit (ATD circuit) detects when an external address transitions and generates a short pulse by detecting it in the summator circuit. In addition, it is a circuit well known in the art as a structure for making and using a new pulse signal required for the operation of the semiconductor memory device using this.

1 is a block diagram illustrating a configuration of an address transition detection circuit of a semiconductor memory device according to the related art. As shown in FIG. 1, the conventional address transition detection circuit includes a short pulse amplifying means 210 and a word line tracking pulse generating means 300. The short pulse amplifying means 210 includes first and second inverting means 10 and 40, first and second delay means 20 and 50 consisting of a plurality of inverters, and a plurality of decoding means 30. , 50). Although not shown in the drawing, the short pulse amplifying unit 210 receives a pulse signal SPi output from a summator circuit and delays it by the delay time by the first and second delay means 20 and 50. The amplified pulse signal SPG is output.

The first inverting means 10 for inverting and outputting the short pulse SPi (where i is a positive integer) output from the summator and the signal receiving the signal output from the first inverting means 10 The first NAND gate G1 connected to each input terminal of the first delay means 20 internally generates a pulse amplified by a delay time by the first delay means 20. The second inverting means 40, the second delaying means 50, and the second decoding means 60 also output the SPG signal delayed and amplified by the above operation. The word line tracking pulse generating means 300 charges the third inverting means 70, the third delay means 80, and the node 1 of the third delay means 80 to the power supply voltage Vcc. And a precharge means (90) composed of a PMOS transistor (M1) and a decoding means (100). That is, the word line tracking pulse generating means 300 outputs an ATD signal delayed and amplified by the delay time by the third delay means 80.

2 is an operation timing diagram according to the prior art. 1 to 2, the address transition detection operation according to the prior art will be described.

The SPi signal, which is a short pulse, is output from the attenuator circuit not shown by the transition of the input signal to the external input terminal, and the pulse width thereof changes according to the timing of the input signals. When the SPi signal is applied to the short pulse amplifying means 210 shown in FIG. 1, the SPi signal is delayed by a predetermined time by the first and second delay means 20 and 50. At this time, the SPG signal output from the short pulse amplifying means 210 is amplified and output in a form in which a time as much as the SPi signal is delayed is added to the pulse width of the input SPi signal as shown in FIG. 2. . The SPG signal is applied to the word line tracking pulse generating means 300, whereby the delay time of the third delay means 80 is added to obtain an ATD signal having a desired pulse width.

As described above, the conventional ATD circuit uses a method of receiving a short pulse SPi output from a not shown summator circuit and amplifying the width of the input pulse using the short pulse amplifying means 210. However, in such a structure, when an input signal or a noisy input signal shorter than the normal pulse width is applied to the input terminal, the input signal is applied to the first and second delay means 20 and 50 of the short pulse amplifying means 210. In some cases, the inverters do not pass through the inverters I2, I3, I5, and I6 and disappear. As a result, the short pulse amplifying means 210 outputs an SPG signal whose pulse width is not sufficiently amplified by the short pulse amplification means 210 compared to the normal pulse width. The SPG signal, which is not sufficiently amplified, is directly applied to the word line tracking pulse generating means 300. Accordingly, a problem arises in that the ATD signal having a shorter pulse width than the required pulse width is output from the word line tracking pulse generating means 300 in order for the semiconductor memory device to perform a normal operation.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to obtain a pulse signal having a required pulse width by performing a normal operation even if a short input signal or a noisy input signal is applied compared to the normal pulse width. An address transition detection circuit of a semiconductor memory device is provided.

1 is a block diagram showing an address transition detection circuit of a semiconductor memory device according to the prior art;

2 is an operation timing diagram according to the prior art;

3 is a block diagram showing a configuration of an address transition detection circuit of a semiconductor memory device according to the present invention;

4 is a circuit diagram showing a detailed circuit of an address transition detection circuit according to a preferred embodiment of the present invention;

5 is an operation timing diagram according to a preferred embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

100: summator 200: short pulse generator

300: word line tracking pulse generator

According to one aspect of the present invention for achieving the above object, an address transition detection circuit of a semiconductor memory device includes a simmer circuit, a pulse generator, and a word line tracking pulse generator, wherein It receives the applied addresses (where i is a positive integer), detects any change in any one of the addresses, and outputs a first signal having a pulse width. The sort pulse generator receives the first signal and outputs a second signal having a predetermined pulse puck. The word line tracking pulse generator outputs a third signal by increasing a pulse width of the second signal. The short pulse generator comprises: a first inverter for inverting the first signal; A second inverter for inverting the output of the first inverter; A NAND gate having a first input terminal for receiving an output of the first inverter; A resistor having a first terminal to receive an output of the second inverter; Third and fourth inverters of which the resistance is directly connected between the second terminal and the second input terminal of the diffuser NAND gate; A PMOS transistor having a gate receiving the output of the first inverters, a source connected to a power supply voltage and a drain connected to the second terminal of the resistor; And a capacitor coupled between the second terminal of the resistor and the ground voltage.

Such a circuit makes it possible to obtain an ATD signal having a pulse width sufficient to perform a normal operation even when a short input signal or a noisy input signal is applied compared to the normal pulse width.

Reference will now be made in detail with reference to FIGS. 3 to 5 according to an embodiment of the present invention.

In Fig. 3 to Fig. 5, the same reference numerals are given to the components having the same functions as the components shown in Figs.

3 is a block diagram illustrating a configuration of an address transition detection circuit of a semiconductor memory device according to an exemplary embodiment of the present invention. 4 is a circuit diagram showing a detailed circuit of an address transition detection circuit of a semiconductor memory device according to a preferred embodiment of the present invention. Hereinafter, the present invention will be described with reference to FIGS. 3 to 4.

The address transition detection circuit according to the present invention shown in FIG. 3 is composed of a summator circuit 100, a short pulse generator 200, and a word line tracking pulse generator 300. The summator circuit 100 receives the addresses Ai (where i is a positive integer) applied from the outside and changes any one of the addresses Ai (that is, the logic state of the address changes). Is detected, the first signal SPi having a predetermined pulse width is output. The short pulse generator 200 receives the first signal SPi output from the summator circuit 100 and outputs a second signal SPG having a pulse width corresponding to a predetermined delay time. .

As illustrated in FIG. 4, the short pulse generator 200 may include a first inverting means 220, a first delaying means 230, a first precharge means 240, and a decoding means 250. Was done. The first inverting means 220 receives the first signal SPi and receives a fourth signal inverting the phase of the first signal SPi. ), A first inverter I12 is connected between the input terminal 3 to which the first signal SPi is input and the node 2. The first delay means 230 is the fourth signal (output from the first inverting means 220) ) Is input, and the fourth signal () for a predetermined time. ) Is output with delay. The first delay means 230 includes second to fourth inverters I13, I14, and I15, a first resistor R2, and a first capacitor C2 as shown in the drawing. .

The first precharge means 240 is the fourth signal (output from the first inverting means 220) Node 1 of the first delay means 230 is charged to the power supply voltage Vcc level in response to the " 1 " The first precharge means 240 includes a PMOS transistor M2 having a channel connected between the power supply terminal 1 to which the power supply voltage Vcc is applied and the node 1 and a gate terminal connected to the node 2. . The first decoding means 250 is the fourth signal (output from the first inverting means 220) ) And the fifth signal D _S1 output from the first delay means 230, the two signals ( And outputs a second signal (SPG), decodes the D _S1). In addition, the first decoding unit 250 includes a first NAND gate G4 and a fifth inverter I16.

As shown in FIGS. 3 and 4, the word line tracking pulse generator 300 receives the second signal SPG output from the short pulse generator 200 and receives the second signal (SPG). The pulse width of the SPG is made longer by a length corresponding to a predetermined time to output the third signal ADT _OUT . As illustrated in FIG. 4, the word line tracking pulse generator 300 may include a second inverting means 310, a second delaying means 320, a second precharge means 330, and a second decoding means. 340. The second inverting means 310 receives the second signal SPG and inverts the phase of the second signal SPG. ) The second inverting means 310 includes a sixth inverter I17 connected between the input terminal 4 and the node 4 to which the second signal SPG is input. The second delay means 320 is a sixth signal (output from the second inverting means 310) ) Is inputted to the sixth signal for a predetermined time. ) Is output with delay. The second delay means 320 includes seventh and eighth inverters I18 and I19, a second resistor R3, and a second capacitor C3 connected as shown in the drawing.

The second precharge means 330 is the sixth signal (output from the second inverting means 310) Node 3 of the second delay means 320 is charged to the power supply voltage Vcc level. The second precharge means 330 includes a PMOS transistor M3 having a channel connected between the power supply terminal 1 and the node 4 (N4) and a gate terminal connected to the node 3 (N3). The second decoding means 340 is the sixth signal (output from the second inverting means 310) ) And the seventh signal D _S2 output from the second delay means 320, the two signals ( , D _S2 ) and outputs the third signal ADT _OUT decoded. The second output means 340 includes a second NAND gate G5 and ninth and tenth inverters I20 and I21 connected as shown in the drawing.

5 is an operation timing diagram according to the present invention. Referring to Figures 3 to 5, the address transition detection operation according to the present invention will be described.

As a result of the transition of the input signal applied to the external input terminal, the SPi signal generated by the summator 100 is applied to the short pulse generator 200. The precharge means 240 of the short pulse generator 200 receiving the SPi signal transitioned from a low level to a high level is enabled. That is, since the SPi signal is at a high level, the first inverting means 220 is used. The signal transitions to a low level. Therefore, the PMOS transistor M2 of the precharge means 240 is turned on to charge the node 1 of the first delay means 230 to the power supply voltage Vcc level. When the SPi signal transitions from the high level to the low level, the charges of the voltage of the node 2 (N2) of the first delay means 230, that is, the capacitor C2, are stored in the resistor R2 and the inverter INV3. Is discharged to ground voltage. That is, the inverter I13 of the high level The signal is applied and the node 1 is discharged by switching to the ground terminal 2 to which the ground voltage Vss is applied. Therefore, the first delay means 230 outputs the D _S1 signal in which the pulse width of the SPi signal is increased by the discharge time.

As a result, the low level output from the first inversion means 220 As shown in FIG. 4, the SPG signal of the short pulse is output through the decoding means 250 receiving the signal and the _DS signal output from the first delay means 230. That is, the D _S1 signal and the Only in a section where the signal is at a high level, the output of the NAND gate G4 is at a low level. The SPG signal of the new short pulse in which the output signal of the NAND gate G4 is inverted by the inverter I16 is output. This is applied to the word line tracking pulse generator 300 to generate an ATDout signal having a normal desired pulse width and used for various circuits of the semiconductor memory device.

According to the present invention, when an input signal having a short pulse width or a noise input signal is input to the input terminal from the outside, an abnormal short pulse is output. In addition, even when the abnormal short pulse is applied to the short pulse generator 200, the PMOS transistor M2 of the precharge unit 240 first before the NAND gate G4 of the first decoding unit 250 operates. It will work. Accordingly, the PMOS transistor M4 operates normally in any input signal capable of operating the NAND gate G4, so that an input signal is generated in the paths of the inverters I13, I14, and I15 of the first delay means 230. It is not destroyed. As a result, the normal short pulse SPG is generated from the short pulse generator 200 and applied to the word line tracking pulse generator 300 to output a desired ATD signal having a normal pulse width. It will work.

As described above, the short pulse generator for generating a new short pulse between the summator and the word line tracking pulse generator is implemented. As a result, even if an input signal having a short pulse width or a noisy input signal is input from the outside, the new short pulse can be generated through the short pulse generator. Therefore, even if a short input signal or a noisy input signal is applied compared to the normal pulse width, an ATD signal having a required pulse width can be obtained.

Claims (1)

It receives the addresses Ai (where i is a positive integer) applied from the outside. A summator circuit (100) for outputting a first signal (SPi) having a predetermined pulse width when a logic state of at least one of the addresses (Ai) is changed; A short pulse generator 200 which receives the first signal SPi and outputs a second signal SPG having a predetermined pulse width; An address transition detection circuit of a semiconductor memory device including a word line tracking pulse generator 300 for outputting a third signal ADTout longer than a pulse width of the second signal SPG; The short pulse generator 200 A first inverter I12 for inverting the first signal SPi; A second inverter (I13) for inverting the output of the first inverter (I12); A NAND gate G4 having a first input terminal for receiving an output of the first inverter I12; A resistor (R2) having a first terminal for receiving the output of the second inverter (I13); Third and fourth inverters I14 and I15 connected in series between a second terminal of the resistor R2 and a second input terminal of the NAND gate G4; A PMOS transistor (M2) having a gate that receives the output of the first inverter (I12), a source connected to a power supply voltage, and a drain connected to a second terminal of the resistor (R2); And a capacitor (C2) coupled between the second terminal of the resistor (R2) and a ground voltage.