KR970067359A

KR970067359A - The address transition detection circuit

Info

Publication number: KR970067359A
Application number: KR1019960007313A
Authority: KR
Inventors: 김효동; 박춘성
Original assignee: 문정환; Lg 반도체주식회사
Priority date: 1996-03-19
Filing date: 1996-03-19
Publication date: 1997-10-13
Also published as: KR100199096B1

Abstract

본 발명은 어드레스 신호의 천이수에 관계없이 일정한 펄스폭을 갖는 어드레스 천이 검출신호(ATDS)를 만들어 출력하도록 구성된 메모리의 어드레스 천이 검출회로(ATD)에 관한 것으로, 그 구성은 다수의 노아회로와, 상기 다수의 노아회로에서 출력하는 각각의 신호를 인가받는 제1낸드회로와, 상기 제1낸드회로에서 출력하는 신호를 반전시키는 제1인버터와, 상기 제1인버터의 출력신호를 수정의 제1시간 만큼 지연시키는 제1지연회로와, 상기 제1지연회로의 출력신호를 소정의 제2시간 만큼 지연시키는 제2지연회로와, 상기 제2지연회로에서 출력하는 신호를 반전시키는 제2인버터와, 상기 제1지연회로에서 출력하는 신호와 상기 제2인버터에서 출력하는 신호를 각각 제1입력단자와 제2입력단자로 인가받는 제N+1노아회로로 이루어진다. 특히, 상기 제1지연회로는 입력된 신호의 상승시점을 소정의 시간(T₁)만큼 지연시키고, 제2지연회로는 입력된 신호의 상승시점 및 하강시점을 각각 소정의 시간(T₂)만큼 지연시켜 출력하도록 구성된다.The present invention relates to an address transition detection circuit (ATD) of a memory configured to generate and output an address transition detection signal (ATDS) having a constant pulse width irrespective of the number of transitions of an address signal, A first inverter for inverting a signal output from the first NAND circuit; a second inverter for inverting the output signal of the first inverter to a first time A second delay circuit for delaying an output signal of the first delay circuit by a predetermined second time, a second inverter for inverting a signal output from the second delay circuit, And an (N + 1) -th NOA circuit which receives the signal output from the first delay circuit and the signal output from the second inverter to the first input terminal and the second input terminal, respectively. In particular, the first delay circuit delays the rising time of the input signal by a predetermined time (T ₁ ), and the second delay circuit outputs the rising time and the falling time of the input signal by a predetermined time (T ₂ ) And output it with delay.

Description

The address transition detection circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명에 따른 메모리의 어드레스 천이 검출회도로, 제4도는 상기 제3도에 도시된 제1지연회로를 도시한 구성회로도, 제5도는 상기 제3도에 도시된 제2지연회로도를 도시한 구성회로도.3 is a circuit diagram showing the address transition detection of the memory according to the present invention, FIG. 4 is a circuit diagram showing the first delay circuit shown in FIG. 3, FIG. 5 is a circuit diagram showing the second delay circuit shown in FIG. Fig.

Claims

A plurality of NOR circuits (NOR ₁ -NOR _N ); A first NAND circuit NAND ₁ receiving the signals output from the plurality of NOR circuits NOR ₁ -NOR _N ; A first inverter (INV ₁ ) for inverting a signal output from the first NAND circuit; A first delay circuit (Delay ₁ ) for delaying the output signal of the first inverter by a predetermined first time; A second delay circuit (Delay ₂ ) for delaying the output signal of the first delay circuit by a predetermined second time; A second inverter (INV ₂ ) for inverting a signal output from the second delay circuit; (N + 1) th NOA circuit (N + 1) circuit for receiving and processing the signal output from the first delay circuit (Delay ₁ ) and the signal output from the second inverter (INV ₂ ) to the first input terminal and the second input terminal, respectively NOR _{< M + 1 >} ).

The address transition detection circuit of claim 1, wherein the first delay circuit delays the rising edge of the input signal by a predetermined time (T ₁ ) and outputs the delayed signal.

The address transition detection circuit according to claim 1, wherein the first delay circuit is configured to delay the rising time and the falling time of the input signal by a predetermined time (T ₂ ), respectively.

※ Note: It is disclosed by the contents of the first application.