KR970055596A - Glitch Rejection Circuit - Google Patents

Glitch Rejection Circuit Download PDF

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Publication number
KR970055596A
KR970055596A KR1019950064419A KR19950064419A KR970055596A KR 970055596 A KR970055596 A KR 970055596A KR 1019950064419 A KR1019950064419 A KR 1019950064419A KR 19950064419 A KR19950064419 A KR 19950064419A KR 970055596 A KR970055596 A KR 970055596A
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KR
South Korea
Prior art keywords
glitch
circuit
clock signal
generated
input
Prior art date
Application number
KR1019950064419A
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Korean (ko)
Other versions
KR100204010B1 (en
Inventor
신동우
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950064419A priority Critical patent/KR100204010B1/en
Publication of KR970055596A publication Critical patent/KR970055596A/en
Application granted granted Critical
Publication of KR100204010B1 publication Critical patent/KR100204010B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

본 발명은 글리치가 발생되는 소정의 회로에 적용되는 글리치 제거 회로에 있어서 상기 글라치가 발생되는 회로에 입력되는 입력데이타(A,B)에 따라 글리치가 발생되지 않을 위치에 클럭 신호를 발생시키는 클럭 신호발생수단(10); 및 상기 클럭 신호 발생수단으로부터의 클럭 신호에 따라 상기 글리치가 발생되는 회로의 출력 데이타를 래치하는 저장수단(20)을 구비하는 것을 특징으로 하는 글리치 제거 회로에 관한 것으로 입력 데이타의 변화에 의한 글리치의 발생을 방지할 수 있어 안장된 회로 설계를 용이하게 할 수 있도록 한다.The present invention provides a clock signal for generating a clock signal at a position where a glitch will not be generated according to input data (A, B) input to a circuit in which the glaciation is generated in a glitch removing circuit applied to a predetermined circuit in which the glitch is generated. Generating means (10); And storage means (20) for latching output data of the circuit in which the glitch is generated in response to a clock signal from the clock signal generating means. It can be prevented from occurring to facilitate the design of the saddle circuit.

Description

글리치 제거 회로Glitch Rejection Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 디코더에 적용한 본 발명의 일실시예에 따른 글리치 제거 회로의 블록 구성도.1 is a block diagram of a glitch cancellation circuit according to an embodiment of the present invention applied to a decoder.

Claims (5)

글리치가 발생되는 소정의 회로에 적용되는 글리치 제거 회로에 있어서 상기 글라치가 발생되는 회로에 입력되는 입력데이타에 따라 글리치가 발생되지 않을 위치에 클럭 신호를 발생시키는 클럭 신호발생수단; 및 상기 클럭 신호 발생수단으로부터의 클럭 신호에 따라 상기 글리치가 발생되는 회로의 출력 데이타를 래치하는 저장수단을 구비하는 것을 특징으로 하는 글리치 제거 회로.A glitch removal circuit applied to a predetermined circuit in which glitch is generated, comprising: clock signal generation means for generating a clock signal at a position where glitch will not be generated according to input data input to the circuit in which the glitch is generated; And storage means for latching output data of a circuit in which the glitch is generated in accordance with a clock signal from the clock signal generating means. 제1항에 있어서 상기 저장수단은 상기 클럭 신호 발생 수단으로부터의 클럭 신호에 따라 상기 글리치가 발생되는 회로의 출력 각각을 래치하며 상기 리셋 회로를 리셋 단자로 입력받는 다수의 플립플롭인 것을 특징으로 하는 글리치 제거 회로.The method of claim 1, wherein the storage means is a plurality of flip-flops for latching each of the output of the circuit in which the glitch is generated in accordance with the clock signal from the clock signal generating means and receiving the reset circuit to the reset terminal Glitch elimination circuit. 제1항 또는 제2항에 있어서 상기 클럭신호 발생수단은 상기 리렛신호 및 상기 글리치가 발생되는 회로의 입력 데이타 각각의 에지를 검출하는 다수의 에지 검출수단;상기 검출수단 각각의 출력을 입력으로 하는 부정 논리합 게이트를 구비하는 것을 특징으로 하는 글리치 제거 회로.The clock signal generating means according to claim 1 or 2, wherein the clock signal generating means comprises: a plurality of edge detecting means for detecting an edge of each of the input data of the circuit in which the relet signal and the glitch are generated; A glitch cancellation circuit comprising a negative AND gate. 제3항에 있어서 상기 에지 검출수단은 상기 리셋 신호 및 상기 글리치가 발생되는 회로의 입력 데이타가 천이할 때마다 하나의 펄스를 발생시키는 것을 특징으로 하는 글리치 제거 회로.4. The glitch removing circuit according to claim 3, wherein the edge detecting means generates one pulse each time the reset signal and the input data of the circuit in which the glitch is generated transition. 제4항에 있어서 상기 에지 검출수단은 입력되는 신호를 반전시키는 지연인버터;상기 지연 인버터의 출력과 상기 입력되는 신호를 두 입력으로 하는 배타적 논리합 게이트를 각각 구비하는 것을 특징으로 하는 글리치 제거 회로.5. The glitch elimination circuit according to claim 4, wherein the edge detecting means comprises a delay inverter for inverting an input signal; an exclusive logic sum gate having two inputs of the output of the delay inverter and the input signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950064419A 1995-12-29 1995-12-29 Glitch removal circuit KR100204010B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950064419A KR100204010B1 (en) 1995-12-29 1995-12-29 Glitch removal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950064419A KR100204010B1 (en) 1995-12-29 1995-12-29 Glitch removal circuit

Publications (2)

Publication Number Publication Date
KR970055596A true KR970055596A (en) 1997-07-31
KR100204010B1 KR100204010B1 (en) 1999-06-15

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ID=19446907

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950064419A KR100204010B1 (en) 1995-12-29 1995-12-29 Glitch removal circuit

Country Status (1)

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KR (1) KR100204010B1 (en)

Also Published As

Publication number Publication date
KR100204010B1 (en) 1999-06-15

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