KR19980039919A - Address Transition Detection Circuit of Semiconductor Memory Device - Google Patents

Abstract

The present invention relates to a semiconductor memory device. More particularly, the present invention relates to an address transition detection circuit of a semiconductor memory device which detects a transition of external addresses and outputs a pulse signal having a predetermined period using the same. A summator circuit that receives the applied addresses, detects any change in any one of the addresses, and outputs a first signal having a predetermined pulse width; A short pulse generator for receiving the first signal output from the summator circuit and outputting a second signal having a pulse width corresponding to a predetermined delay time; And a word line tracking pulse generator configured to receive the second signal output from the short pulse generator and output a third signal which further delays the second signal by a predetermined time.

Description

(A circuit of detecting address transition of semiconductor device)

The present invention relates to a semiconductor memory device, and more particularly, to an address transition detection circuit of a semiconductor memory device which detects a transition of external addresses and outputs a pulse signal having a predetermined period using the same.

In an asynchronous semiconductor memory device, an address transition detector circuit (ATD circuit) detects when an external address transitions and generates a short pulse by detecting it in the summator circuit. In addition, it is a circuit well known in the art as a structure for making and using a new pulse signal required for the operation of the semiconductor memory device using this.

1 is a block diagram illustrating a configuration of an address transition detection circuit of a semiconductor memory device according to the related art. As shown in FIG. 1, the conventional address transition detection circuit includes a short pulse amplifying means 210 and a word line tracking pulse generating means 300. The short pulse amplifying means 210 includes first and second inverting means 10 and 40, first and second delay means 20 and 50 consisting of a plurality of inverters, and a plurality of decoding means 30. , 50). Although not shown in the drawing, the short pulse amplifying unit 210 receives a pulse signal SPi output from a summator circuit and delays it by the delay time by the first and second delay means 20 and 50. The amplified pulse signal SPG is output.

The first inverting means 10 for inverting and outputting the short pulse SPi (where i is a positive integer) output from the summator and the signal receiving the signal output from the first inverting means 10 The first NAND gate G1 connected to each input terminal of the first delay means 20 internally generates a pulse amplified by a delay time by the first delay means 20. The second inverting means 40, the second delaying means 50, and the second decoding means 60 also output the SPG signal delayed and amplified by the above operation. The word line tracking pulse generating means 300 charges the third inverting means 70, the third delay means 80, and the node 1 of the third delay means 80 to the power supply voltage Vcc. And a precharge means (90) composed of a PMOS transistor (M1) and a decoding means (100). That is, the word line tracking pulse generating means 300 outputs an ATD signal delayed and amplified by the delay time by the third delay means 80.

2 is an operation timing diagram according to the prior art. 1 to 2, the address transition detection operation according to the prior art will be described.

The SPi signal, which is a short pulse, is output from the attenuator circuit not shown by the transition of the input signal to the external input terminal, and the pulse width thereof changes according to the timing of the input signals. When the SPi signal is applied to the short pulse amplifying means 210 shown in FIG. 1, the SPi signal is delayed by a predetermined time by the first and second delay means 20 and 50. At this time, the SPG signal output from the short pulse amplifying means 210 is amplified and output in a form in which a time as much as the SPi signal is delayed is added to the pulse width of the input SPi signal as shown in FIG. 2. . The SPG signal is applied to the word line tracking pulse generating means 300, whereby the delay time of the third delay means 80 is added to obtain an ATD signal having a desired pulse width.

As described above, the conventional ATD circuit uses a method of receiving a short pulse SPi output from a not shown summator circuit and amplifying the width of the input pulse using the short pulse amplifying means 210. However, in such a structure, when an input signal or a noisy input signal shorter than the normal pulse width is applied to the input terminal, the input signal is applied to the first and second delay means 20 and 50 of the short pulse amplifying means 210. In some cases, the inverters do not pass through the inverters I2, I3, I5, and I6 and disappear. As a result, the short pulse amplifying means 210 outputs an SPG signal whose pulse width is not sufficiently amplified by the short pulse amplification means 210 compared to the normal pulse width. The SPG signal, which is not sufficiently amplified, is directly applied to the word line tracking pulse generating means 300. Accordingly, a problem arises in that the ATD signal having a shorter pulse width than the required pulse width is output from the word line tracking pulse generating means 300 in order for the semiconductor memory device to perform a normal operation.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to obtain a pulse signal having a required pulse width by performing a normal operation even if a short input signal or a noisy input signal is applied compared to the normal pulse width. An address transition detection circuit of a semiconductor memory device is provided.

1 is a block diagram showing an address transition detection circuit of a semiconductor memory device according to the prior art;

2 is an operation timing diagram according to the prior art;

3 is a block diagram showing a configuration of an address transition detection circuit of a semiconductor memory device according to the present invention;

4 is a circuit diagram showing a detailed circuit of an address transition detection circuit according to a preferred embodiment of the present invention;

5 is an operation timing diagram according to a preferred embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

100: summator 200: short pulse generator

300: word line tracking pulse generator

According to an aspect of the present invention for achieving the above object, it receives an address applied from the outside, detects any change in any one of the addresses and outputs a first signal having a predetermined pulse width A summarizer circuit; A short pulse generator for receiving the first signal output from the summator circuit and outputting a second signal having a pulse width corresponding to a predetermined delay time; And a word line tracking pulse generator configured to receive the second signal output from the short pulse generator, and output a third signal which further delays the second signal by a predetermined time.

In this embodiment, the short pulse generator comprises: first inverting means for receiving the first signal and outputting a fourth signal inverting the phase of the first signal; First delay means for receiving the fourth signal output from the first inverting means and delaying and outputting the fourth signal by a predetermined time; First precharge means for charging node 1 of the first delay means to a power supply voltage level in response to the fourth signal output from the first inverting means; And a first decoding means for receiving the fourth signal outputted from the first inverting means and the fifth signal outputted from the first delaying means, and outputting the second signal obtained by decoding the two signals.

In this embodiment, the first inverting means comprises a first inverter connected between a node 2 and an input terminal to which the first signal is input.

In this embodiment, the first delay means is composed of second to fourth inverters, a first resistor, and a first capacitor.

In this embodiment, the first precharge means includes a first PMOS transistor having a channel connected between a power supply terminal to which a power supply voltage is applied and the node 1, and a gate terminal connected to the node 2.

In this embodiment, the first decoding means comprises a first NAND gate and a fifth inverter.

The word line tracking pulse generation unit may include: second inverting means for receiving the second signal and outputting a sixth signal in which the phase of the second signal is inverted; Second delay means for receiving the sixth signal output from the second inverting means and delaying and outputting the sixth signal for a predetermined time; Second precharge means for charging node 3 of the second delay means to a power supply voltage level in response to the sixth signal output from the second inverting means; And a second decoding means for receiving the sixth signal output from the second inverting means and the seventh signal output from the second delay means and outputting the third signal obtained by decoding the two signals.

In this embodiment, the second inverting means comprises a sixth inverter connected between the input terminal to which the second signal is input and the node 4.

In this embodiment, the second delay means consists of seventh and eighth inverters, a second resistor, and a second capacitor.

In this embodiment, the second precharge means includes a second PMOS transistor having a channel connected between the power supply terminal and the node 3 and a gate terminal connected to the node 4.

In this embodiment, said second decoding means consists of a second NAND gate and ninth and tenth inverters.

Such a circuit makes it possible to obtain an ATD signal having a pulse width sufficient to perform a normal operation even when a short input signal or a noisy input signal is applied compared to the normal pulse width.

Reference will now be made in detail with reference to FIGS. 3 to 5 according to an embodiment of the present invention.

In Fig. 3 to Fig. 5, the same reference numerals are given to the components having the same functions as the components shown in Figs.

3 is a block diagram illustrating a configuration of an address transition detection circuit of a semiconductor memory device according to an exemplary embodiment of the present invention. 4 is a circuit diagram illustrating a detailed circuit of an address transition detection circuit of a semiconductor memory device according to an exemplary embodiment of the present invention. Hereinafter, the present invention will be described with reference to FIGS. 3 to 4.

The address transition detection circuit according to the present invention shown in FIG. 3 is composed of a summator circuit 100, a short pulse generator 200, and a word line tracking pulse generator 300. The summator circuit 100 receives the addresses Ai (where i is a positive integer) applied from the outside, detects any one of the addresses Ai and changes a predetermined pulse width. The first signal SPi is outputted. The short pulse generator 200 receives the first signal SPi output from the summator circuit 100 and outputs a second signal SPG having a pulse width corresponding to a predetermined delay time. .

As illustrated in FIG. 4, the short pulse generator 200 may include a first inverting means 220, a first delaying means 230, a first precharge means 240, and a decoding means 250. Was done. The first inverting means 220 receives the first signal SPi and receives a fourth signal inverting the phase of the first signal SPi. ), A first inverter I12 is connected between the input terminal 3 to which the first signal SPi is input and the node 2. The first delay means 230 is the fourth signal (output from the first inverting means 220) ) Is input, and the fourth signal () for a predetermined time. ) Is output with delay. The first delay unit 230 includes second to fourth inverters I13, I14, and I15, a first resistor R2, and a first capacitor C2.

The first precharge means 240 is the fourth signal (output from the first inverting means 220) Node 1 of the first delay means 230 is charged to the power supply voltage Vcc level in response to the " 1 " The first precharge means 240 includes a PMOS transistor M2 having a channel connected between the power supply terminal 1 to which the power supply voltage Vcc is applied and the node 1 and a gate terminal connected to the node 2. . The first decoding means 250 is the fourth signal (output from the first inverting means 220) ) And the fifth signal D _S1 output from the first delay means 230, the two signals ( And outputs a second signal (SPG), decodes the D _S1). In addition, the first decoding unit 250 includes a first NAND gate G4 and a fifth inverter I16.

As shown in FIGS. 3 and 4, the word line tracking pulse generator 300 receives the second signal SPG output from the short pulse generator 200 and receives the second signal (SPG). The third signal ADT _OUT is further output by delaying the SPG by a predetermined time. As illustrated in FIG. 4, the word line tracking pulse generator 300 may include a second inverting means 310, a second delaying means 320, a second precharge means 330, and a second decoding means. 340. The second inverting means 310 receives the second signal SPG and inverts the phase of the second signal SPG. ) The second inverting means 310 includes a sixth inverter I17 connected between the input terminal 4 and the node 4 to which the second signal SPG is input. The second delay means 320 is a sixth signal (output from the second inverting means 310) ) Is inputted to the sixth signal for a predetermined time. ) Is output with delay. In addition, the second delay means 320 includes the second delay means 320 including seventh and eighth inverters I18 and I19, a second resistor R3, and a second capacitor C3. .

The second precharge means 330 is the sixth signal (output from the second inverting means 310) Node 3 of the second delay means 320 is charged to the power supply voltage Vcc level. The second precharge means 330 includes a PMOS transistor M3 having a channel connected between the power supply terminal 1 and the node 3 and a gate terminal connected to the node 4. The second decoding means 340 is the sixth signal (output from the second inverting means 310) ) And the seventh signal D _S2 output from the second delay means 320, the two signals ( , D _S2 ) and outputs the third signal ADT _OUT decoded. The second decoding means 340 includes a second NAND gate G5 and ninth and tenth inverters I20 and I21.

5 is an operation timing diagram according to the present invention. Referring to Figures 3 to 5, the address transition detection operation according to the present invention will be described.

As a result of the transition of the input signal applied to the external input terminal, the SPi signal generated by the summator 100 is applied to the short pulse generator 200. The precharge means 240 of the short pulse generator 200 receiving the SPi signal transitioned from a low level to a high level is enabled. That is, since the SPi signal is at a high level, the first inverting means 220 is used. The signal transitions to a low level. Therefore, the PMOS transistor M2 of the precharge means 240 is turned on to charge the node 1 of the first delay means 230 to the power supply voltage Vcc level. When the SPi signal transitions from the high level to the low level, the node 1 of the first delay means 230 is discharged through the inverter I13. That is, the inverter I13 of the high level The signal is applied and the node 1 is discharged by switching to the ground terminal 2 to which the ground voltage Vss is applied. Therefore, the first delay means 230 outputs the D _S1 signal in which the pulse width of the SPi signal is increased by the discharge time.

As a result, the low level output from the first inversion means 220 As shown in FIG. 4, the SPG signal of the short pulse is output through the decoding means 250 receiving the signal and the _DS signal output from the first delay means 230. That is, the D _S1 signal and the Only in a section where the signal is at a high level, the output of the NAND gate G4 is at a low level. The SPG signal of the new short pulse in which the output signal of the NAND gate G4 is inverted by the inverter I16 is output. This is applied to the word line tracking pulse generator 300 to generate an ATDout signal having a normal desired pulse width and used for various circuits of the semiconductor memory device.

According to the present invention, when an input signal having a short pulse width or a noise input signal is input to the input terminal from the outside, an abnormal short pulse is output. In addition, even when the abnormal short pulse is applied to the short pulse generator 200, the PMOS transistor M2 of the precharge unit 240 first before the NAND gate G4 of the first decoding unit 250 operates. It will work. Accordingly, the PMOS transistor M4 operates normally in any input signal capable of operating the NAND gate G4, so that an input signal is generated in the paths of the inverters I13, I14, and I15 of the first delay means 230. It is not destroyed. As a result, the normal short pulse SPG is generated from the short pulse generator 200 and applied to the word line tracking pulse generator 300 to output a desired ATD signal having a normal pulse width. It will work.

As described above, the short pulse generator for generating a new short pulse between the summator and the word line tracking pulse generator is implemented. As a result, even if an input signal having a short pulse width or a noisy input signal is input from the outside, the new short pulse can be generated through the short pulse generator. Therefore, even if a short input signal or a noisy input signal is applied compared to the normal pulse width, an ATD signal having a required pulse width can be obtained.

Claims (11)

Receives a first signal SPi having a predetermined pulse width by receiving an address Ai (where i is a positive integer) applied from the outside and detecting any one of the addresses Ai. A summator circuit 100 for outputting; A short pulse generator 200 receiving the first signal SPi output from the simmer circuit 100 and outputting a second signal SPG having a pulse width corresponding to a predetermined delay time; Word line tracking that receives the second signal SPG output from the short pulse generator 200 and outputs a third signal ATD _OUT which further delays the second signal SPG by a predetermined time. An address transition detection circuit of a semiconductor memory device including a pulse generator 300. The method of claim 1, The short pulse generator 200 receives the first signal SPi and receives a fourth signal in which the phase of the first signal SPi is inverted. A first reversing means (220) for outputting; The fourth signal outputted from the first inverting means 220 ) Is input, and the fourth signal () for a predetermined time. First delay means 230 for delaying and outputting; The fourth signal outputted from the first inverting means 220 First precharge means (240) for charging node 1 of the first delay means (230) to a power supply voltage (Vcc) level in response to the " The fourth signal outputted from the first inverting means 220 ) And the fifth signal D _S1 output from the first delay means 230, the two signals ( And a first decoding means (250) for outputting the second signal (SPG) decoded (D _S1 ). The method of claim 2, And the first inverting means (220) comprises a first inverter (I12) connected between an input terminal (3) to which the first signal (SPi) is input and a node (2). The method of claim 2, And the first delay means (230) comprises second to fourth inverters (I13, I14, I15), a first resistor (R2), and a first capacitor (C2). The method of claim 2, The first precharge means 240 is a first PMOS transistor M2 having a channel connected between the power supply terminal 1 to which the power supply voltage Vcc is applied and the node 1 and a gate terminal connected to the node 2. An address transition detection circuit of a configured semiconductor memory device. The method of claim 2, And the first decoding means (250) comprises a first NAND gate (G4) and a fifth inverter (I16). The method of claim 1, The word line tracking pulse generator 300 receives the second signal SPG and inverts the phase of the second signal SPG. Second inverting means (310) for outputting; The sixth signal output from the second inverting means 310 ( ) Is inputted to the sixth signal for a predetermined time. Second delay means (320) for delaying and outputting; The sixth signal output from the second inverting means 310 ( Second precharge means (330) for charging node 3 of the second delay means (320) to a power supply voltage (Vcc) level in response to the " The sixth signal output from the second inverting means 310 ( ) And the seventh signal D _S2 output from the second delay means 320, the two signals ( And second decoding means (340) for outputting the third signal (ATD _OUT ) decoded D _S2 ). The method of claim 7, wherein And the second inverting means (310) comprises a sixth inverter (I17) connected between an input terminal (4) to which the second signal (SPG) is input and a node (4). The method of claim 7, wherein And the second delay means (320) comprises seventh and eighth inverters (I18, I19), a second resistor (R3), and a second capacitor (C3). The method of claim 7, wherein The second precharge means 330 transitions an address of a semiconductor memory device including a second PMOS transistor M3 having a channel connected between the power supply terminal 1 and the node 3 and a gate terminal connected to the node 4. Detection circuit. The method of claim 7, wherein And the second decoding means (340) comprises a second NAND gate (G5) and ninth and tenth inverters (I20, I21).