KR960043516A - High Speed Data Output Buffer - Google Patents

High Speed Data Output Buffer Download PDF

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Publication number
KR960043516A
KR960043516A KR1019950010730A KR19950010730A KR960043516A KR 960043516 A KR960043516 A KR 960043516A KR 1019950010730 A KR1019950010730 A KR 1019950010730A KR 19950010730 A KR19950010730 A KR 19950010730A KR 960043516 A KR960043516 A KR 960043516A
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KR
South Korea
Prior art keywords
logical operation
operation means
output buffer
data
high speed
Prior art date
Application number
KR1019950010730A
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Korean (ko)
Inventor
권기원
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950010730A priority Critical patent/KR960043516A/en
Publication of KR960043516A publication Critical patent/KR960043516A/en

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Abstract

본 발명의 고속 데이타 출력 버퍼는, 고저항 퓨즈를 사용하여 풀-업 및 풀-다운 트랜지스터의 사이즈를 조정하므로 데이타출력버퍼가 E.D.O 기능을 가질 경우에 풀-다운 트랜지스터의 면적을 노멀한 신호를 출력할 경우보다 크게 하여 출력 데이타가 하이레벨에서 로우레벨로의 전이시 잡음을 감소하며 데이타 처리 시간을 빠르게 하는 이점을 제공한다.The high-speed data output buffer of the present invention adjusts the size of the pull-up and pull-down transistors by using a high resistance fuse, and thus outputs a normal signal for the area of the pull-down transistor when the data output buffer has an EDO function. This results in greater output, which reduces the noise at the transition from high level to low level and provides faster data processing time.

Description

고속 데이타 출력 버퍼High Speed Data Output Buffer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 실시예에 따른 고속 데이타 출력 버퍼의 회로도.2 is a circuit diagram of a high speed data output buffer according to an embodiment of the present invention.

Claims (5)

E.D.O 신호발생회로와, 상기 E.D.O 신호발생회로로부터의 신호 및 리드라인으로부터의 데이타를 논리 연산하는 제1논리연산수단과, 상기 E.D.O 신호발생회로로부터의 신호 및 리드라인으로부터의 데이타를 논리 연산하는 제2논리연산수단과, 제1전원전압 및 출력라인 사이에 접속되어 상기 제1논리연산수단으로부터의 신호에 따라 절환동작을 수행하는 제1피모스트랜지스터와, 제1전원전압 및 출력라인 사이에 접속되어 리드라인으로부터의 데이타에 따라 절환동작을 수행하는 제2피모트랜지스터와, 제2전원전압 및 출력라인 사이에 접속되어 리드라인으로부터의 데이타에 따라 절환동작을 수행하는 제1엔모스트랜지스터와, 제2전원전압 및 출력라인 사이에 접속되어 상기 제2논리연산수단으로부터의 신호에 따라 절환동작을 수행하는 제2엔모스트랜지스터를 구비한 것을 특징으로 하는 고속 데이타 출력 버퍼.A first logical operation means for performing a logical operation on an EDO signal generation circuit, a signal from the EDO signal generation circuit and data from a lead line, and a first operation for logically calculating data from the signal and lead line from the EDO signal generation circuit. (2) a connection between a logic operation means, a first power supply voltage and an output line, and a first MOS transistor for performing a switching operation according to a signal from said first logic operation means, and a connection between a first power supply voltage and an output line; A second MOS transistor for performing a switching operation according to the data from the lead line, a first NMOS transistor connected between the second power supply voltage and the output line and performing a switching operation according to the data from the lead line; A second NMOS transistor connected between a second power supply voltage and an output line to perform a switching operation in accordance with a signal from the second logical operation means; And a high speed data output buffer. 제1항에 있어서, 상기 제1논리연산수단 및 제2논리연산수단 사이에 접속되어 리드라인으로부터의 데이타와 출력인에이블신호를 논리연산하는 제3논리연산 수단을 추가로 구비한 것을 특징으로 하는 고속 데이타 출력 버퍼.2. The apparatus according to claim 1, further comprising a third logical operation means connected between the first logical operation means and the second logical operation means to logically operate on the data and the output enable signal from the lead line. Fast data output buffer. 제1항에 있어서, 상기 제1논리연산수단이 NAND게이트인 것을 특징으로 하는 고속 데이타 출력 버퍼.2. The high speed data output buffer as claimed in claim 1, wherein said first logical operation means is a NAND gate. 제1항에 있어서, 상기 제2논리연산수단이 NOR게이트인 것을 특징으로 하는 고속 데이타 출력 버퍼.A high speed data output buffer as claimed in claim 1, wherein said second logical operation means is a NOR gate. 제1항에 있어서, 상기 제3논리연산수단이 상기 리드라인으로부터의 데이타와 출력인에이블신호를 논리연산하는 NOR 게이트와, 상기 리드라인으로부터의 데이타와 출력인에이블신호를 논리연산하는 NAND게이트를 포함하는 것을 특징으로 하는 고속 데이타 출력 버퍼.2. The NOR gate according to claim 1, wherein the third logical operation means performs a logical operation on the data and output enable signal from the lead line, and a NAND gate on the logical operation of the data and output enable signal from the lead line. And a high speed data output buffer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950010730A 1995-05-02 1995-05-02 High Speed Data Output Buffer KR960043516A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950010730A KR960043516A (en) 1995-05-02 1995-05-02 High Speed Data Output Buffer

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Application Number Priority Date Filing Date Title
KR1019950010730A KR960043516A (en) 1995-05-02 1995-05-02 High Speed Data Output Buffer

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KR960043516A true KR960043516A (en) 1996-12-23

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KR1019950010730A KR960043516A (en) 1995-05-02 1995-05-02 High Speed Data Output Buffer

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468686B1 (en) * 1997-08-28 2005-03-16 삼성전자주식회사 Fusing circuit
KR100482361B1 (en) * 1997-09-10 2005-09-14 삼성전자주식회사 Open Drain and Pull-Up Circuitry

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468686B1 (en) * 1997-08-28 2005-03-16 삼성전자주식회사 Fusing circuit
KR100482361B1 (en) * 1997-09-10 2005-09-14 삼성전자주식회사 Open Drain and Pull-Up Circuitry

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