KR960042753A - Wordline control circuit - Google Patents

Wordline control circuit Download PDF

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Publication number
KR960042753A
KR960042753A KR1019950011737A KR19950011737A KR960042753A KR 960042753 A KR960042753 A KR 960042753A KR 1019950011737 A KR1019950011737 A KR 1019950011737A KR 19950011737 A KR19950011737 A KR 19950011737A KR 960042753 A KR960042753 A KR 960042753A
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KR
South Korea
Prior art keywords
voltage
line
detecting
pmos transistor
data bit
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KR1019950011737A
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Korean (ko)
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KR100373339B1 (en
Inventor
이종협
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950011737A priority Critical patent/KR100373339B1/en
Publication of KR960042753A publication Critical patent/KR960042753A/en
Application granted granted Critical
Publication of KR100373339B1 publication Critical patent/KR100373339B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

본 발명은 SRAM(Static RAM)셀의 쓰기 동작시 데이타 비트라인 DB(Data Bit line)와 반전된 데이타 비트라인(/Data Bit line)의 전압을 감지하여 이중 하나의 라인이 일정전압 이하로 떨어지면 검출신호를 발생시켜 워드라인을 디스에이블 시키도록 한 워드라인 제어 회로에 관한 것으로, 데이타 비트(이하, DB라 칭함)라인의 전압변화를 검출하는 제1전압 검출수단; 반던된 데이타 비트(이하,라 칭함)라인의 전압변화를 검출하는 제2전압 검출수단; 상기 제1 및 제2전압 검출수단의 출력을 입력받아 워드라인을 제어하기 위한 일정전압 검출신호를 출력하는 논리연산수단을 구비하는 것을 특징으로 하여 정적전류의 흐름을 차단하고 불필요한 전렬소모를 줄일 수 있으며, 상기 DB,라인의 변화를 검출한 일정전압 검출신호를 쓰기 드라이버에 인가하여 쓰기 드라이버에 존재하는 정적전류 경로를 끊어줄 수 있는 효과가 있다.According to the present invention, a data bit line (DB) and an inverted data bit line are inverted during a write operation of a static RAM (SRAM) cell. The word line control circuit detects a voltage of (/ Data Bit line) and generates a detection signal when one of the lines falls below a certain voltage to disable the word line. The data bit (hereinafter referred to as DB) First voltage detecting means for detecting a voltage change of the line; Rounded data bits (hereinafter, Second voltage detecting means for detecting a voltage change of a line; Logic operation means for receiving the output of the first and second voltage detection means for outputting a constant voltage detection signal for controlling the word line, it is possible to block the flow of the static current and reduce unnecessary heat consumption The DB, The constant voltage detection signal which detects the change of the line is applied to the write driver, thereby cutting off the static current path existing in the write driver.

Description

워드라인 제어 회로Wordline control circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2B도는 본 발명에 따른 워드라인 제어 회로도, 제5도는 본 발명이 적용되는 로컬 X 디코더의 회로도.2A to 2B are a word line control circuit diagram according to the present invention, and FIG. 5 is a circuit diagram of a local X decoder to which the present invention is applied.

Claims (3)

데이타 비트(이하, DB라 칭함)라인의 전압변화를 검출하는 제1전압 검출수단; 반전된 데이타 비트(이하,라 칭함)라인의 전압변화를 검출하는 제2전압 검출수단; 및 상기 제1 및 제2전압 검출수단의 출력을 입력받아 워드라인을 제어하기 위한 일정전압 검출신호를 출력하는 논리연산수단을 구비하는 것을 특징으로 하는 워드라인 제어 회로.First voltage detecting means for detecting a voltage change of a data bit (hereinafter referred to as DB) line; Inverted data bits (hereinafter, Second voltage detecting means for detecting a voltage change of a line; And logic operation means for receiving outputs of the first and second voltage detection means and outputting a constant voltage detection signal for controlling the word line. 제1항에 있어서, 상기 논리연산수단에 연결되어 DB,라인이 일정전압 이하로 떨어진 후, 소정 전압(Vb)에서 셀에 쓰기 되도록 출력에 얼마간의 지연을 유발하는 지연부를 더 포함하는 것을 특징으로 하는 워드라인 제어 회로.The method of claim 1, further comprising: a DB connected to the logical operation means; And a delay unit for causing some delay in the output to write to the cell at a predetermined voltage (V b ) after the line falls below a certain voltage. 제1항 또는 제2항에 있어서, 상기 제1 및 제2전압 검출수단은, 입력단로부터 입력전압(INPUT)을 게이트로 입력받고 전원전압(Vcc)을 소스로 입력받는 제1PMOS 트랜지스터; 상기 입력전압(INPUT)을 게이트로 입력받고 소스가 상기 제1PMOS 트랜지스터의 드레인에 연결되며 드레인이 출력단에 연결되는 제2PMOS 트랜지스터; 상기 출력단에 게이트가 연결되고 소스가 상기 제1PMOS 트랜지스터의 드레인에 연결되며 드레인이 접지되는 제3PMOS트랜지스터를 구비하는 풀업부와, 상기 입력전압(INPUT)을 게이트로 입력받고 소스가 접지되며 드레인이 출력단에 연결되는 NMOS 트랜지스터로 구성되는 풀다운부를 구비하는 것을 특징으로 하는 워드라인 제어 회로.3. The display device of claim 1, wherein the first and second voltage detection means comprise: a first PMOS transistor configured to receive an input voltage INPUT from a input terminal as a gate and a power supply voltage Vcc as a source; A second PMOS transistor receiving the input voltage INPUT as a gate, a source connected to a drain of the first PMOS transistor, and a drain connected to an output terminal; A pull-up part including a third PMOS transistor having a gate connected to the output terminal, a source connected to a drain of the first PMOS transistor, and a drain being grounded; And a pull-down section comprising an NMOS transistor connected to the word line control circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950011737A 1995-05-12 1995-05-12 Word line control circuit of sram KR100373339B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950011737A KR100373339B1 (en) 1995-05-12 1995-05-12 Word line control circuit of sram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950011737A KR100373339B1 (en) 1995-05-12 1995-05-12 Word line control circuit of sram

Publications (2)

Publication Number Publication Date
KR960042753A true KR960042753A (en) 1996-12-21
KR100373339B1 KR100373339B1 (en) 2004-03-06

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KR1019950011737A KR100373339B1 (en) 1995-05-12 1995-05-12 Word line control circuit of sram

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422812B1 (en) * 1997-06-30 2004-05-24 주식회사 하이닉스반도체 Semiconductor memory device for minimizing constant current in write operation
KR100665831B1 (en) * 2000-08-08 2007-01-09 삼성전자주식회사 Low power embodiment method of semiconductor device
KR100670709B1 (en) * 2004-11-01 2007-01-17 주식회사 하이닉스반도체 Semiconductor memory device with low power consumption

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100422812B1 (en) * 1997-06-30 2004-05-24 주식회사 하이닉스반도체 Semiconductor memory device for minimizing constant current in write operation
KR100665831B1 (en) * 2000-08-08 2007-01-09 삼성전자주식회사 Low power embodiment method of semiconductor device
KR100670709B1 (en) * 2004-11-01 2007-01-17 주식회사 하이닉스반도체 Semiconductor memory device with low power consumption

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