KR930010992A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR930010992A
KR930010992A KR1019910020914A KR910020914A KR930010992A KR 930010992 A KR930010992 A KR 930010992A KR 1019910020914 A KR1019910020914 A KR 1019910020914A KR 910020914 A KR910020914 A KR 910020914A KR 930010992 A KR930010992 A KR 930010992A
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South Korea
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signal
terminal
output
voltage
inputting
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KR1019910020914A
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Korean (ko)
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KR940008720B1 (en
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민경열
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김광호
삼성전자 주식회사
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Publication of KR930010992A publication Critical patent/KR930010992A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)

Abstract

본 발명은 반도체 메모리 장치의 분리트랜지스터의 제어전압 발생장치에 관한 것으로, 종래기술에서는 상기 제어전압이 Vpp레벨로 프리차아지되어 칩의 액티브 동작시에 상기 Vpp레벨에서 풀스윙 동작을 하게 됨에 따라 전류소비의 문제뿐만 아니라 데이타의 센싱동작이 지연되었으나, 본 발명에서는 상기 제어전압이 프리차아지 상태에서는 Vcc레벨로 인가되고 액티브 상태에서는 Vpp레벨 및 Vss레벨(=Ov)로 인가되어 전류소비의 감소와 데이타의 센서동작을 고속으로 수행할 수 있게 된다.The present invention relates to a control voltage generator of an isolation transistor of a semiconductor memory device. In the prior art, the control voltage is precharged to Vpp level so that a full swing operation occurs at the Vpp level during the active operation of the chip. In addition to the consumption problem, the data sensing operation is delayed. However, in the present invention, the control voltage is applied at the Vcc level in the precharge state and at the Vpp level and the Vss level (= Ov) in the active state, thereby reducing the current consumption The sensor operation of the data can be performed at high speed.

Description

반도체 메모리 장치Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도(A),(B)는 본 발명에 의한 øISO발생장치의 회로도.4A and 4B are circuit diagrams of the? ISO generator according to the present invention.

제5도는 본 발명에 의한 øBLSI(øBSLj)발생장치의 회로도.5 is a circuit diagram of a? BLSI (? BSLj) generator according to the present invention.

Claims (6)

비트라인을 서로 공유하는 제1 및 제2메모리 어레이 블록을 가지는 반도체 메모리 장치에 있어서, 소정의 어드레스 버퍼에서 출력되는 어드레스에 의해 구동되는 블록선택신호를 입력하여 상기 제1 및 제2메모리 어레이블록이 모두 비선택화될시에는 소정의 제1신호를 출력하고 상기 제1 또는 제2메모리 어레이 블록이 선택화될 시에는 소정의 제2 및 제3신호를 출력하는 분리트랜지스터 제어전압 발생장치를 구비함을 특징으로 하는 반도체 메모리 장치.A semiconductor memory device having first and second memory array blocks sharing bit lines with each other, wherein the first and second memory array blocks are input by inputting a block selection signal driven by an address output from a predetermined address buffer. And a separate transistor control voltage generator for outputting a predetermined first signal when all are unselected, and outputting predetermined second and third signals when the first or second memory array block is selected. A semiconductor memory device, characterized in that. 제1항에 있어서, 상기 제1신호가 칩의 동작전원전압(Vcc)임과, 상기 제2 및 제3신호가 각각 상기 동작전원전압(Vcc)보다 높은 승압전압(Vpp)(또는 Ov전압) 및 Ov전압(또는 상기 승압전압(Vpp))임을 특징으로 하는 반도체 메모리 장치.The voltage supply voltage Vpp (or Ov voltage) according to claim 1, wherein the first signal is an operating power supply voltage Vcc of the chip, and the second and third signals are respectively higher than the operating power supply voltage Vcc. And an Ov voltage (or the boosted voltage Vpp). 제1항에 있어서, 상기 분리트랜지스터 제어전압 발생장치가 상기 제1 및 제2메모리 어레이 블록을 선택하는 제1 및 제2블록 선택신호(øBLSi,øBLSj)를 입력하는 입력단(20)과, 상기 입력단(20)의 출력신호를 입력하여 상기 제1 또는 제2 또는 제3신호를 출력하는 출력단(30)과, 상기 출력단(30)의 출력신호를 상기 제1 또는 제2메모리 어레이 블록이 선택될시에 상기 제2 또는 제3신호로 만드는 승압전압단(40)으로 이루어짐을 특징으로 하는 반도체 메모리 장치.The input terminal 20 of claim 1, wherein the isolation transistor control voltage generator inputs first and second block selection signals øBLSi and øBLSj for selecting the first and second memory array blocks. When the output terminal 30 for inputting the output signal of 20 and outputting the first, second or third signal, and the output signal of the output terminal 30, the first or second memory array block is selected. And a boosted voltage terminal (40) made of the second or third signal. 제3항에 있어서, 상기 입력단(20)이 상기 제1 및 제2블록선택신호(øBLSi,øBLSj)를 입력하는 노아회로로 구성된 제1입력단(20A)과, 상기 제1 또는 제2블록선택신호(øBLSi,øBLSj)를 입력하는 드라이버로 구성된 제2입력단(20B)로 이루어짐을 특징으로 하는 반도체 메모리 장치.4. The first input terminal 20A of claim 3, wherein the input terminal 20 comprises a NOR circuit for inputting the first and second block selection signals? BLSi and? BLSj, and the first or second block selection signal. and a second input terminal (20B) constituted by a driver for inputting (øBLSi, øBLSj). 제4항에 있어서, 상기 출력단(30)이 상기 제1입력단(20A)의 출력신호 및 상기 제2입력단(20B)의 출력신호를 입력하는 씨모오스 인버터(31,32)로 이루어짐을 특징으로 하는 반도체 메모리 장치.The method of claim 4, wherein the output terminal 30 is characterized in that the CMOS inputs (31, 32) for inputting the output signal of the first input terminal (20A) and the output signal of the second input terminal (20B). Semiconductor memory device. 제5항에 있어서, 상기 승압전압단(40)이 상기 제2 또는 제1블록 선택신호(øBLSi)(øBLSj)를 입력하는 드라이버(41,42,43)와, 게이트가 상기 드라이버(41,42,43)의 출력단에 접속되고 채널의 양단이 소정의 승압전압단(Vpp) 및 상기 출력단(30)의 출력라인(33) 사이에 형성되는 풀업트랜지스터(44)로 이루어짐을 특징으로 하는 반도체 메모리 장치.6. The driver of claim 5, wherein the step-up voltage terminal 40 inputs the second or first block selection signal? BLSi (? BLSj), and the gate has the drivers 41,42. And a pull-up transistor 44 which is connected to an output terminal of the power supply line 43 and both ends of the channel are formed between a predetermined boosted voltage terminal Vpp and an output line 33 of the output terminal 30. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910020914A 1991-11-22 1991-11-22 Semiconductor memory device KR940008720B1 (en)

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KR1019910020914A KR940008720B1 (en) 1991-11-22 1991-11-22 Semiconductor memory device

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Application Number Priority Date Filing Date Title
KR1019910020914A KR940008720B1 (en) 1991-11-22 1991-11-22 Semiconductor memory device

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KR930010992A true KR930010992A (en) 1993-06-23
KR940008720B1 KR940008720B1 (en) 1994-09-26

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KR100488542B1 (en) * 2002-10-21 2005-05-11 삼성전자주식회사 semiconductor memory device of enhancing bitline precharge time

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