KR970017637A - Sense Amplifier Control Circuit of Semiconductor Memory Device - Google Patents

Sense Amplifier Control Circuit of Semiconductor Memory Device Download PDF

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Publication number
KR970017637A
KR970017637A KR1019950030111A KR19950030111A KR970017637A KR 970017637 A KR970017637 A KR 970017637A KR 1019950030111 A KR1019950030111 A KR 1019950030111A KR 19950030111 A KR19950030111 A KR 19950030111A KR 970017637 A KR970017637 A KR 970017637A
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KR
South Korea
Prior art keywords
signal
sense amplifier
sensing
control circuit
output
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KR1019950030111A
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Korean (ko)
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KR0172419B1 (en
Inventor
한용주
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김광호
삼성전자 주식회사
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Priority to KR1019950030111A priority Critical patent/KR0172419B1/en
Publication of KR970017637A publication Critical patent/KR970017637A/en
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Publication of KR0172419B1 publication Critical patent/KR0172419B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

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  • Dram (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 반도체 메모리장치의 센스앰프 제어회로에 관한 것으로, 특히 초기의 라이트동작시 발생되는 센스 앰프의 센싱동작을 소정시간 차단하는 반도체 메모리장치의 센스앰프 제어회로에 관한 것이다.The present invention relates to a sense amplifier control circuit of a semiconductor memory device, and more particularly, to a sense amplifier control circuit of a semiconductor memory device which blocks a sensing operation of a sense amplifier generated during an initial write operation for a predetermined time.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래의 경우 입력동작시 비트라인쌍에서는 원치않는 데이타충돌이 발생하게 된다. 이에 따라 센싱시간이 지연되고 데이타 충돌로 인한 데이타 정보를 상쇄하기 위한 전류방전동작이 실행되어 전력소비가 심하게 된다.In the conventional case, an unwanted data collision occurs in a pair of bit lines during an input operation. As a result, the sensing time is delayed and the current discharge operation for canceling the data information due to the data collision is executed, resulting in high power consumption.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

상기와 같은 문제점을 해소하기 위하여 본 발명에서는 센셍제어회로를 구비하여 초기의 라이트동작시 센스앰프의 센싱동작을 소정시간 차단하게 된다.In order to solve the above problems, the present invention includes a sensing control circuit to block the sensing operation of the sense amplifier during the initial write operation for a predetermined time.

4. 발명의 중요한 용도4. Important uses of the invention

고속의 입력동작을 수행하고 저전력소비 및 안정적인 입력동작을 수행하는 반도체 메모리장치.A semiconductor memory device performing a high speed input operation, low power consumption and stable input operation.

Description

반도체 메모리장치의 센스앰프 제어회로Sense Amplifier Control Circuit of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 실시예에 따른 센스앰프 제어회로의 사용상태를 보여주는 도면,2 is a view showing a state of use of the sense amplifier control circuit according to an embodiment of the present invention,

제3도는 본 발명의 다른 실시예에 따른 센스앰프 제어회로의 사용상태를 보여주는 도면.3 is a view showing a state of use of the sense amplifier control circuit according to another embodiment of the present invention.

Claims (5)

소정의 워드라인과 한쌍의 비트라인사이에 접속되고 소정의 데이타를 입출력하기 위한 다수의 메모리셀과, 상기 비트라인쌍사이에 접속되어 액세스동작시 상기 비트라인 쌍의 전압차이를 감지증폭하는 하나이상의 센스앰프와, 상기 비트라인쌍과 접속된 한쌍의 입출력라인과, 컬럼어드레스 스트로브신호에 응답하여 라이트 드라이버 구동신호를 출력하는 라이트 드라이버 구동회로와, 상기 라이트 드라이버 구동신호에 응답하여 입력 데이타를 상기 입출력라인쌍으로 전송하는 라이트 드라이버와, 상기 컬럼어드레스 스트로브신호에 동기되는 컬럼선택신호에 의해 도통되어 상기 입출력라인쌍과 상기 비트라인쌍을 선택적으로 연결하는 컬럼선택게이트들을 구비하는 반도체 메모리장치의 센스앰프 제어회로에 있어서, 소정의 제1신호에 응답하여 상기 센스앰프를 구동하기 위한 센스앰프 구동신호를 출력하는 센스앰프 구동회로와; 상기 라이트 드라이버 구동신호에 응답하여 소정의 펄스신호를 출력하는 펄스신호발생수단과, 상기 펄스신호발생수단의 출력신호와 상기 센스앰프 구동신호를 논리조합하는 센싱차단수단으로 구성되고 라이트 동작시 센스앰프의 초기의 센싱동작을 소정시간 차단하는 센싱제어신호를 출력하는 센싱제어회로와; 상기 센스앰프와 전원전압단자사이에 접속되고 상기 펄스신호에 의한 센싱제어신호에 응답하므로써 전원전압을 차단하여 초기의 센싱동작이 소정시간 차단되는 센싱인에이블회로로 구성됨을 특징으로 하는 반도체 메모리장치의 센스앰프 제어회로.One or more memory cells connected between a predetermined word line and a pair of bit lines and connected to input and output predetermined data, and one or more connected between the bit line pairs to sense and amplify a voltage difference of the pair of bit lines during an access operation. A sense driver, a pair of input / output lines connected to the pair of bit lines, a write driver driving circuit for outputting a write driver driving signal in response to a column address strobe signal, and input data in response to the write driver driving signal; A sense amplifier of a semiconductor memory device having a write driver for transmitting a line pair and column select gates electrically connected by a column select signal synchronized with the column address strobe signal to selectively connect the input / output line pair and the bit line pair In the control circuit, in response to the first predetermined signal A sense amplifier driving circuit for outputting a sense amplifier driving signal for driving the sense amplifier; Pulse signal generating means for outputting a predetermined pulse signal in response to the write driver driving signal, and sensing blocking means for logically combining the output signal of the pulse signal generating means and the sense amplifier driving signal, A sensing control circuit for outputting a sensing control signal to block an initial sensing operation of the predetermined time period; And a sensing enable circuit connected between the sense amplifier and the power supply voltage terminal and blocking the power supply voltage in response to the sensing control signal by the pulse signal to block the initial sensing operation for a predetermined time. Sense amplifier control circuit. 제1항에 있어서, 상기 소정의 제1신호가 로우어드레스 스트로브신호임을 특징으로 하는 반도체 메모리장치의 센스앰프 제어회로.2. The sense amplifier control circuit of claim 1, wherein the first predetermined signal is a low address strobe signal. 제1항에 있어서, 상기 펄스발생수단이 상기 라이트 드라이버 구동신호를 입력하는 직렬접속된 소정갯수의 인버터들과, 상기 인버터들의 출력과 상기 라이트 드라이버 구동신호를 부논리곱하는 낸드게이트로 구성되어 소정의 펄스신호를 출력하는 숏펄스발생기임을 특징으로 하는 반도체 메모리장치의 센스앰프 제어회로.2. The predetermined number of inverters of claim 1, wherein the pulse generating means comprises a predetermined number of inverters connected in series for inputting the write driver driving signal, and a NAND gate that negatively multiplies the output of the inverters and the write driver driving signal. And a short pulse generator for outputting a pulse signal. 제1항에 있어서, 상기 센싱차단수단이 상기 펄스발생수단의 출력신호와 상기 센스앰프 구동신호를 부논리곱하는 낸드게이트와, 상기 낸드게이트의 출력을 반전하는 인버터로 구성됨을 특징으로 하는 반도체 메모리장치의 센스앰프 제어회로.2. The semiconductor memory device according to claim 1, wherein the sensing blocking means comprises a NAND gate that negatively multiplies the output signal of the pulse generating means and the sense amplifier driving signal, and an inverter that inverts the output of the NAND gate. Sense amplifier control circuit. 제1항에 있어서, 상기 센싱인에이블회로가 엔형센스앰프의 구동단자와 접지전압단자사이에 채널이 접속되고 상기 센싱제어신호가 게이트에 접속되는 엔모오스 트랜지스터와, 상기 센싱제어신호를 반전하는 인버터와, 피형센스앰프의 구동단자와 전원전압단자사이에 채널이 접속되고 상기 인버터의 출력단에 게이트가 접속되는 피모오스 트랜지스터로 구성됨을 특징으로 하는 반도체 메모리장치의 센스앰프 제어회로.The inverter of claim 1, wherein the sensing enable circuit comprises an NMOS transistor having a channel connected between a driving terminal of an N-type sense amplifier and a ground voltage terminal, and the sensing control signal connected to a gate, and an inverter for inverting the sensing control signal. And a PMOS transistor having a channel connected between a driving terminal of the type sense amplifier and a power supply voltage terminal, and a gate connected to an output terminal of the inverter. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950030111A 1995-09-14 1995-09-14 Sense amp. control circuit of semiconductor memory device KR0172419B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950030111A KR0172419B1 (en) 1995-09-14 1995-09-14 Sense amp. control circuit of semiconductor memory device

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KR970017637A true KR970017637A (en) 1997-04-30
KR0172419B1 KR0172419B1 (en) 1999-03-30

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100418582B1 (en) * 1996-06-29 2004-05-07 주식회사 하이닉스반도체 Sense amplifier
KR100596767B1 (en) * 1999-06-29 2006-07-04 주식회사 하이닉스반도체 Sense amplifier control circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100924343B1 (en) * 2007-10-29 2009-11-02 주식회사 하이닉스반도체 Semiconductor Memory Device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100418582B1 (en) * 1996-06-29 2004-05-07 주식회사 하이닉스반도체 Sense amplifier
KR100596767B1 (en) * 1999-06-29 2006-07-04 주식회사 하이닉스반도체 Sense amplifier control circuit

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