KR930014574A - Data Output Buffer with Preset Circuit - Google Patents

Data Output Buffer with Preset Circuit Download PDF

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Publication number
KR930014574A
KR930014574A KR1019910024802A KR910024802A KR930014574A KR 930014574 A KR930014574 A KR 930014574A KR 1019910024802 A KR1019910024802 A KR 1019910024802A KR 910024802 A KR910024802 A KR 910024802A KR 930014574 A KR930014574 A KR 930014574A
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KR
South Korea
Prior art keywords
pull
circuit
output
data
transition
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KR1019910024802A
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Korean (ko)
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KR940008137B1 (en
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전태수
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김광호
삼성전자 주식회사
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Priority to KR1019910024802A priority Critical patent/KR940008137B1/en
Publication of KR930014574A publication Critical patent/KR930014574A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

본 발명은 반도체 메모리 장치에서 특히 메모리 셀에서 독출된 데이타를 칩 외부로 출력시키는 데이타 출력버퍼에 관한 것으로, 본 발명에 의한 데이타 출력 버퍼는 외부 어드레스의 천이에 의한 상기 출력데이타의 천이동작시에 상기 외부 어드레스의 천이동작을 미리 검출하여 상기 출력데이타가 천이하기 전에 상기 출력데이타의 전압레벨을 상승 또는 하강시키어 전원전압단 또는 접지전압단에서 발생되는 노이즈를 최대한 억제하기 위하여, 상기 출력데이타와 소정의 어드레스 천이 검출회로(ATD)에 의해서 인에이블되는 신호(Φ1)를 각각 입력하는 노아회로(11) 및 낸드회로(22)와 상기 노아회로(11)아 낸드회로(22)의 각 출력신호에 의해 제어되어 이로부터 바로 상기 출력데이타의 저압레벨을 천이동작전에 미리 풀업 또는 풀다운 시키는 풀업 및 풀다운 회로(10,12)(20,23)로 이루어지는 프리세트회로(100)를 구비하므로서, 구성이 콤팩트(compact)하고 고속동작을 가지며, 소정의 데이타 출력동작시에 소비전류의 발생이 최대한 억제되어 노이즈의 발생이 최소화되고 출력단에서 데이타의 천이시간이 빠르게 이루어지므로서, 데이타 출력버퍼의 동작을 안정화시켜 신뢰성을 향상시키는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output buffer for outputting data read out of a memory cell, in particular from a memory cell, to the outside of the chip. In order to detect a transition operation of an external address in advance and raise or lower the voltage level of the output data before the output data is transitioned, to minimize noise generated at the power supply terminal or the ground voltage terminal. By the output signals of the NOR circuit 11 and the NAND circuit 22 and the NOR circuit 11 and the NAND circuit 22 which respectively input the signal Φ 1 enabled by the address transition detection circuit ADT. Pull-ups and pull-ups, which are controlled to pull up or pull down the low pressure level of the output data immediately before the transition operation. By providing the preset circuit 100 which consists of operation circuits 10 and 12 (20 and 23), it is compact in structure and has a high speed operation, and the generation of consumption current is suppressed as much as possible in the predetermined data output operation. Therefore, the occurrence of noise is minimized and the transition time of the data is fast at the output stage, thereby improving the reliability by stabilizing the operation of the data output buffer.

Description

프리세트회로를 구비하는 데이타 출력버퍼Data Output Buffer with Preset Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 데이타 출력버퍼의 일 실시예.2 is an embodiment of a data output buffer according to the present invention.

제4도는 본 발명에 의한 데이타 출력버퍼의 다른 실시예.4 is another embodiment of a data output buffer according to the present invention.

Claims (4)

서로 상보적으로 개폐동작이 이루어지는 출력용 풀업 및 풀다운 트랜지스터로 이루어지는 출력단을 가지고 소정의 데이타를 칩 외부로 출력하는 데이타 출력버퍼에 있어서, 외부 어드레스의 천이에 의한 상기 출력데이타의 천이동작시에 상기 외부 어드레스의 천이동작을 미리 검출하여 상기 출력데이타가 천이하기 전에 상기 출력데이타의 전압레벨을 상승 또는 하강시키어 전원전압단 또는 접지전압단에서 발생되는 노이즈를 최대한 억제하기 위하여, 상기 출력데이타와 소정의 어드레스 천이 검출회로(ATD)에 의해서 인에이블되는 신호(Φ1)를 각각 입력하는 노아회로(11) 및 낸드회로(22)와 상기 노아회로(11)와 낸드회로(22)의 각 출력신호에 의해 제어되어 이로부터 바로 상기 출력데이타의 전압레벨을 천이동작전에 미리 풀업 또는 풀다운 시키는 풀업 및 풀다운 회로(10,12)(20,23)로 이루어지는 프리세트회로(100)를 구비함을 특징으로 하는 데이타 출력버퍼.A data output buffer having an output stage consisting of an output pull-up and a pull-down transistor that complementarily open and close to each other, and outputting predetermined data to the outside of the chip, wherein the external address is changed during a transition operation of the output data due to a transition of an external address. In order to suppress the noise generated at the power supply voltage terminal or the ground voltage terminal by increasing or decreasing the voltage level of the output data before detecting the transition operation in advance, the output data and the predetermined address transition It is controlled by the NOR circuit 11 and the NAND circuit 22 and the output signals of the NOR circuit 11 and the NAND circuit 22 which respectively input the signal Φ 1 enabled by the detection circuit ADT. From this, the pull to pull up or pull down the voltage level of the output data before the transition operation And a data output buffer, characterized in that the pull-down circuit having a preset circuit 100 is composed of a (10, 12) (20,23). 제1항에 있어서, 상기 프리세트회로(100)의 인에이블동작은 상기 제어신호(Φ1)가 인가되는 동안만 이루어짐을 특징으로 하는 데이타 출력버퍼.The data output buffer according to claim 1, wherein the enable operation of the preset circuit (100) is performed only while the control signal (Φ1) is applied. 서로 상보적으로 개폐동작이 이루어지는 출력용 풀업 및 풀다운 트랜지스터로 이루어지는 출력단을 가지고소정의 데이타를 칩 외부로 출력하는 데이타 출력버퍼에 있어서, 외부 어드레스의 천이에 의한 상기 출력데이타의 천이동작시에 상기 외부 어드레스의 천이동작을 미리 검출하여 상기 출력데이타가 천이하기 전에 상기 출력데이타의 전압레벨을 상승 또는 하강시키어 저원전압단 또는 접지전압단에서 발생되는 노이즈를 최대한 억제하기 위하여, 상기 출력데이타와 소정의 어드레스 천이 검출회로(ATD)에 의해서 인에이블되는 신호(Φ1)를 각각 입력하는 노아회로(11) 및 낸드회로(22)와, 상기 노아회로(11) 및 낸드회로(22)의 각 출력신호에 의해 제어되기 이로부터 바로 상기 출력데이타의 전압레벨을 천이동작전에 미리 풀 업 또는 풀다운 시키는 풀업 및 풀다운 회로(10,12)(20,23)와, 상기 풀업 및 풀다운 회로(10,12)(20,23)의 각 인에이블 동작시 발생되는 노이즈의 발생을 감소시키는 풀업 및 풀다운(R1,R2)로 이루어지는 프리세트회로(100')를 구비함을 특징으로 하는 데이타 출력버퍼.A data output buffer having an output stage consisting of an output pull-up and a pull-down transistor in which opening and closing operations are complementary to each other, and outputting predetermined data to the outside of the chip, wherein the external address is changed during the transition operation of the output data due to a transition of an external address. In order to suppress the noise generated at the low source voltage terminal or the ground voltage terminal by increasing or decreasing the voltage level of the output data before detecting the transition operation in advance, the output data and the predetermined address transition Controlled by the NOR circuit 11 and the NAND circuit 22 for inputting the signal Φ 1 enabled by the detection circuit ADT, and the respective output signals of the NOR circuit 11 and the NAND circuit 22. Immediately after this, the voltage level of the output data is pulled up or pulled down before the transition operation. Pull-up and pull-down (R1) for reducing the generation of noise generated during each enable operation of the up and pull-down circuits (10, 12) (20, 23) and the pull-up and pull-down circuits (10, 12) (20, 23). And a preset circuit (100 ') consisting of R2. 제3항에 있어서, 상기 프리세트회로(100')의 인에이블동작은 상기 제어신호(Φ1)가 인가되는 동안만 이루어짐을 특징으로 하는 데이타 출력버퍼.4. The data output buffer as claimed in claim 3, wherein the enable operation of the preset circuit (100 ') is performed only while the control signal (Φ1) is applied. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910024802A 1991-12-28 1991-12-28 Data output buffer KR940008137B1 (en)

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Application Number Priority Date Filing Date Title
KR1019910024802A KR940008137B1 (en) 1991-12-28 1991-12-28 Data output buffer

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Application Number Priority Date Filing Date Title
KR1019910024802A KR940008137B1 (en) 1991-12-28 1991-12-28 Data output buffer

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KR930014574A true KR930014574A (en) 1993-07-23
KR940008137B1 KR940008137B1 (en) 1994-09-03

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990004896A (en) * 1997-06-30 1999-01-25 김영환 Preset Circuit of Semiconductor Memory Device
KR100239696B1 (en) * 1996-09-13 2000-01-15 김영환 Output buffer circuit of semiconductor device
KR100486119B1 (en) * 1997-11-28 2005-07-07 주식회사 하이닉스반도체 Voltage level shifter of high speed symmetric buffer type semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100239696B1 (en) * 1996-09-13 2000-01-15 김영환 Output buffer circuit of semiconductor device
KR19990004896A (en) * 1997-06-30 1999-01-25 김영환 Preset Circuit of Semiconductor Memory Device
KR100486119B1 (en) * 1997-11-28 2005-07-07 주식회사 하이닉스반도체 Voltage level shifter of high speed symmetric buffer type semiconductor integrated circuit

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KR940008137B1 (en) 1994-09-03

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