KR20010063500A - Power up circuit - Google Patents

Abstract

PURPOSE: A power-up circuit is provided to stably operate even when testing or a supply voltage is lowered, by generating a power-up signal of the first level at initially supplying voltage and generating a power-up signal of the second level lowered than the first level when the supply voltage is stabilized. CONSTITUTION: The power-up circuit includes a detector(200), a detection inverter(210), the first and second buffers(220,230) and an output unit(240). The detector(200) detects the level of a supply voltage(Vext). And the detection inverter(210) outputs the first power-up level signal(pwruph) of a relatively high level, and outputs the second power-up level signal(pwrupl) of a relatively low level in response to the level detection signal outputted from the detector. And then, the first and second buffers(220,230) respectively buffers the first and second power-up level signals. After that, the output unit(240) receives the first and second power-up level signals outputted from the first and second buffers(220,230) and outputs the power signal(pwrup).

Description

Power up circuit {POWER UP CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device, and more particularly to a circuit in which a power supply voltage reaches a constant level without operating the circuit immediately after the power supply voltage is applied from the outside when the power supply voltage is initially applied in a DRAM circuit of the semiconductor memory device. And a power up circuit for operating the circuit.

In general, the semiconductor memory device does not operate in response to the power supply voltage level immediately after the power supply voltage is applied from the outside, but operates after the power supply voltage level rises above a certain level. A power up circuit is provided.

The power-up circuit is designed to prevent the entire memory device from being destroyed by latch-up when the internal circuit operates after the power voltage is applied from the outside before the level of the power voltage is stabilized. Improve the reliability of the whole chip.

The power-up circuit senses the level rise of the power supply voltage applied from the outside at the initial application of the power supply voltage, and outputs a "low" power-up signal up to a predetermined level. The up signal is shifted to " high " and output. On the contrary, when the level of the power supply voltage applied from the outside becomes low, the power-up circuit outputs a "high" power-up signal as it is until a predetermined level, but when the power supply voltage level falls below the predetermined level, the power-up signal of the "low" again. Outputs

The power-up signal is output as a "high" value after the level of the power supply voltage is stabilized, and operates independently in a pipe unit among the internal circuits of the memory, and is mainly used in a circuit requiring an initialization operation.

FIG. 1 is a detailed circuit diagram of a conventional power-up circuit, and includes a detector 100 for detecting a level of a power voltage Vext applied from the outside in response to a predetermined level value, and is output from the detector 100. A plurality of inverters 110, 120, 130 for buffering the level detection signal and outputting a power-up signal pwrup.

In detail, the sensing unit 100 includes a PMOS transistor PM1 having a gate terminal connected to a ground power supply terminal, and receiving a power supply voltage Vext from a source, and a drain and ground power supply of the PMOS transistor PM1. An NMOS transistor NM1 is diode-connected between stages, and the level sensing signal, which is an output signal of the sensing unit, is output from the common drain terminal of the PMOS transistor PM1 and the NMOS transistor NM1.

When the power supply voltage is initially applied, the detection unit 100 senses the level of the power supply voltage applied from the outside and outputs a "high" level detection signal until the power supply voltage level is stabilized. A low level detection signal is output.

In addition, the slope of the level detection signal is slowed down due to the size of the transistor constituting the sensing unit 100 to make the slope sharper in the first inverter 110, and then buffered again through the two inverters 120 and 130. Output a power-up signal pwrup.

FIG. 2 is a graph illustrating a power-up signal pwrup according to a time and a power supply voltage applied from the outside in the power-up circuit of FIG. 1 according to the prior art, when the level of the power supply voltage rises and falls. It can be seen that the level at which the power-up signal pwrup becomes " high " is the same.

In the conventional power-up circuit configured as shown in FIG. 1, since any predetermined level value for detecting the level rise of the power supply voltage Vext, that is, the power-up level is fixed, it is a bump test or an external power supply. When the voltage level becomes unstable and the level of the power supply voltage Vext is lowered, a problem arises in that the power-up signal pwrup falls to "low" and the entire chip cannot be operated.

To solve this problem, if the power-up level is lowered so that a power-up operation occurs at a lower voltage level (i.e., a "high" power-up signal is output at a lower voltage level), an external power supply voltage The problem that the circuit operates before the level is stabilized at the initial application is not solved.

The present invention divides a power-up level for detecting a level rise of a power supply voltage into first and second levels, and generates a power-up signal by using a relatively high first-level power-up level when the initial power-up is applied. After the power supply voltage level is stabilized, the power-up signal is generated by using the power-up level of the relatively low second level, so that the internal circuit can be operated normally even during the test or when the power supply voltage level is lowered. The purpose is to provide a circuit.

1 is a detailed circuit diagram of a conventional power-up circuit.

FIG. 2 is a graph illustrating a power-up signal pwrup according to a time and a power supply voltage applied from the outside in the power-up circuit of FIG. 1 according to the prior art. FIG.

3 is a detailed circuit diagram of a power-up circuit according to an embodiment of the present invention.

4 is a simulation result timing diagram for the power up circuit of FIG.

5 is a detailed circuit diagram of a power up circuit according to another embodiment of the present invention;

6 is a detailed circuit diagram of a power-up circuit according to another embodiment of the present invention.

FIG. 7 is a graph illustrating a power-up signal pwrup according to a power supply voltage applied from time and externally in the power-up circuit of FIGS. 5 and 6.

* Description of the main parts of the drawing

200: detector

210: detection inverter

220, 230: buffering part

240: output unit

320, 420: Slope control unit

The present invention provides a power-up circuit for generating a power-up signal for controlling an internal circuit operation of the semiconductor memory device in response to a level of a power supply voltage applied from the outside in the semiconductor memory device. Sensing means for sensing a level of a power supply voltage; Sensing inverting means for outputting a first power up level signal having a relatively high voltage level value and a second power up level signal having a relatively low voltage level value in response to the level sensing signal output from the sensing means; First and second buffering means for buffering first and second power-up level signals output from the sensing inverting means, each of which includes a plurality of inverting means; And output means for receiving the buffered first and second power up level signals output from the first and second buffering means and outputting the power up signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a detailed circuit diagram of a power-up circuit according to an embodiment of the present invention, which is provided from a detector 200 and a detector 200 for detecting a level of a power voltage Vext applied from the outside. A sensing inverter 210 for outputting a first power up level signal pwruph of a relatively high voltage level value and a second power up level signal pwrupl of a relatively low voltage level value in response to the level sensing signal; Each of the two inverters is configured to buffer the first and second power-up level signals (pwruph, pwrupl) output from the sensing inverter 210, 220 and 230, and the buffering unit 220 An output unit 240 for receiving the buffered first and second power-up level signals pwruph and pwrupl respectively outputted from the output unit, and outputting a final power-up signal pwrup for controlling the operation of the internal circuit according to the power supply voltage level. Is made of.

Specifically, the power up circuit configuration of the present invention will be described.

In the power-up circuit, the sensing unit 200 has the same configuration as that of the sensing unit provided in the conventional power-up circuit, and thus, further description thereof will be omitted.

The sensing inverter 210 receives a power supply voltage Vext from a source as a source and receives a level sensing signal from the sensing unit 200 as a gate, and one side of the sensing inverter 210 receives a level sensing signal from a sensor 200. And an NMOS transistor NM2 connected between the other end of the resistor R1 and the ground power supply terminal and receiving the level sensing signal from the sensing unit 200 as a gate. The first power up level signal pwruph is output from the connection point of the PMOS transistor PM2 and the resistor R1, and the second power up level signal pwrupl is output from the connection point of the resistor R1 and the NMOS transistor NM2. .

The output unit 240 receives the first power-up level signal pwruph and the feedback signal B, which are buffered by the buffering unit 220, and a negative logic gate 241 and a buffering unit 230 that perform negative logic multiplication. And a latch composed of a negative logic gate 242 that receives the second power-up level signal pwrupl buffered at and a feedback signal A and performs a negative logic multiplication, wherein the feedback signal B is a negative logic gate. An output signal of 242, the feedback signal A is an output signal of the negative logic gate 241. In addition, the output unit 240 includes an inverter 243 for inverting a signal output from the negative logic gate 242 and outputting a final power-up signal pwrup.

4 is a timing diagram of a simulation result of the power-up circuit of FIG. 3.

3 and 4, in the power up circuit of the present invention, the second power up level signal pwrupl operates first "high" and then the first power up level signal pwruph goes "high". When the level of the external power voltage rises at the initial power-up, the final power-up signal pwrup follows the first power-up level signal pwruph of a relatively high voltage level, and conversely, the level of the power voltage. In this case, the second power up level signal pwrupl of a relatively low voltage level is followed. Therefore, when the level of the test or other power supply voltage is lowered after the external power supply voltage is stabilized, the final power-up signal is determined by the second power-up level signal pwruph of a relatively low voltage level, thereby normalizing the internal circuit. It can be operated.

5 is a detailed circuit diagram of a power-up circuit according to another embodiment of the present invention, in which the output level of the sensing inverter 310 is "high" to "low" without inserting a separate resistor into the sensing inverter 310. It further comprises a slope control unit 320 for gently controlling the slope when the transition to.

Here, the slope control unit 320 includes a PMOS transistor PM3 connected between the output terminal of the sensing inverter 310 and the power supply voltage terminal vext so that the output level of the sensing inverter 310 is "high" to "low". It is configured to fall relatively late when falling to. Here, the gate of the PMOS transistor PM3 is connected to the output terminal of the inverter 330 for buffering the signal output from the sensing inverter 310.

FIG. 6 is a detailed circuit diagram illustrating a power up circuit according to another embodiment of the present invention. Unlike the embodiment of FIG. 5, the output level of the level detection signal output from the sensing unit 400 is from "high" to "high". It further includes a slope control unit 420 for smoothly controlling the slope when the transition to "low".

Here, the slope control unit 420 has an NMOS transistor NM3 connected between the output terminal of the sensing unit 400 and the ground power supply terminal, so that when the output level of the level detection signal falls from "high" to "low", It was configured to fall late. Here, the gate of the NMOS transistor NM3 receives a feedback input from the signal output from the sensing inverter 310.

FIG. 7 is a graph illustrating a power-up signal pwrup according to a time and a power supply voltage applied from the outside in the power-up circuit of FIGS. 5 and 6.

Referring to the drawings, when the level of the power supply voltage applied from the outside increases, the power-up signal pwrup is enabled at the relatively high voltage level value V1, and when the level of the power supply voltage falls, the relatively low voltage level value is lowered. It can be seen that the power-up signal pwrup is disabled at V2.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention as described above, the power-up level for enabling the power-up signal is changed according to the level of the power supply voltage applied from the outside, so that the power-up level is relatively low after the level of the external power supply voltage is stabilized. Therefore, when the power supply voltage is lowered due to the test during the operation of the chip, the conventional malfunction in which the internal circuit does not operate can be eliminated.

Claims (7)

In the power-up circuit for generating a power-up signal for controlling the operation of the internal circuit of the semiconductor memory device in response to the level of the power supply voltage applied from the outside in the semiconductor memory device, Sensing means for sensing the level of the power supply voltage; Sensing inverting means for outputting a first power up level signal having a relatively high voltage level value and a second power up level signal having a relatively low voltage level value in response to the level sensing signal output from the sensing means; First and second buffering means for buffering first and second power-up level signals output from the sensing inverting means, each of which includes a plurality of inverting means; And Output means for receiving the buffered first and second power up level signals outputted from the first and second buffering means and outputting the power up signal; Power up circuit comprising a. The method of claim 1, wherein the sensing inverting means, A PMOS transistor receiving the power supply voltage as a source and receiving a level sensing signal from the sensing means as a gate; A resistor having one side connected to a drain of the PMOS transistor; And A NMOS transistor connected between the other side of the resistor and a ground power supply terminal and receiving a level sensing signal from the sensing means as a gate; The first power up level signal is output from a common connection terminal of the PMOS transistor and the resistor, and the second power up level signal is output from a common connection terminal of the resistor and the NMOS transistor. . The method of claim 2, wherein the output means, First negative logic means for negatively multiplying the buffered first power-up level signal and the first feedback signal outputted from the first buffering means; Second negative logic means for negatively multiplying the buffered second power-up level signal and the second feedback signal outputted from the second buffering means; And And an inverter which inverts the signal output from the second negative logical means to finally output the power-up signal. And the first feedback signal is a signal fed back from an output end of the second negative logical means and the second feedback signal is a signal fed back from an output end of the first negative logical means. In the power-up circuit for generating a power-up signal for controlling the operation of the internal circuit of the semiconductor memory device in response to the level of the power supply voltage applied from the outside in the semiconductor memory device, Sensing means for sensing the level of the power supply voltage; Sensing inverting means for inverting in response to a level sensing signal output from said sensing means; Buffering means for buffering an inverted level sensing signal output from said sensing inverting means, including a plurality of inverting means; And Slope control means connected to the output terminal of the sensing inverting means for relatively smoothly controlling the slope when the output level of the inverted level sensing signal transitions from "high" to "low" Power up circuit comprising a. The method of claim 4, wherein the slope control means, A PMOS transistor connected between a supply terminal for applying the power supply voltage and an output terminal of the sensing inverting means, and receiving a feedback input of an output signal of an initial inverting means among the plurality of inverting means to a gate; Power up circuit comprising a. In the power-up circuit for generating a power-up signal for controlling the operation of the internal circuit of the semiconductor memory device in response to the level of the power supply voltage applied from the outside in the semiconductor memory device, Sensing means for sensing the level of the power supply voltage; Sensing inverting means for inverting in response to a level sensing signal output from said sensing means; Buffering means for buffering an inverted level sensing signal output from said sensing inverting means, including a plurality of inverting means; And Slope control means connected to the output terminal of the sensing means for relatively smoothly controlling the slope when the output level of the level detection signal transitions from "high" to "low" Power up circuit comprising a. The method of claim 6, wherein the slope control means, An NMOS transistor connected between an output terminal of the sensing means and a ground power supply terminal and receiving a feedback signal of an output signal of the sensing inverting means to a gate. Power up circuit comprising a.