KR100265594B1 - Power-up circuit - Google Patents

Abstract

PURPOSE: A power-up circuit is provided to perform a power-up mode only when a power-up signal is in low state even though a power-up sensor is enabled, so that stable operation is possible regardless of noises. CONSTITUTION: The circuit includes a power-up sensor(10), a power-up enabling part(30), a latch part(40), a capacitor(C1) and a buffering part(20). The power-up sensor(10) senses the power and enables the power-up signal(pwrup) as low state. According to an output signal from the power-up sensor(10) and the feed-back power-up signal(pwrup), the power-up enabling part(30) controls to perform power-up mode only when the power-up signal(pwrup) is in low state. The power voltage from the power-up enabling part(30) is applied to the first node(N1). The latch part(40) between the first and second nodes(N1,N2) latches electric potential of the second node(N2). The capacitor(C1) between the power-up enabling part(30) and a ground terminal stabilizes low state of the power-up signal(pwrup). The buffering part(20) delays electric potential of the second node(N2), and outputs the power-up signal(pwrup).

Description

Power-up circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-circuit of a semiconductor memory device. In particular, it guarantees the output of the low-power section of the power-up signal even under the worst conditions, so that the initial value of each latch is surely set when the power-up signal is set. It guarantees and enables a power-up circuit that can be enabled even if the power shakes violently.

In general, the DRAM operation is reliable only after a certain period of time after an external voltage is applied. The power-up circuit goes to each input buffer when the power is turned on and sets the initial value of the latch. The up signal is generated to control important control signals such as ras (/ RAS) and cascade (/ CAS).

However, in order for the power-up circuit to set each latch value, there must be a section in which the power-up signal is 'low', and the conventional power-up circuit ensures a section in which the power-up signal is 'low'. Since there was no power, the power-up signal was output 'high' at the worst condition, thereby incorrectly setting the initial value of the input buffer and enabling unnecessary signals, thereby causing a large current consumption.

Hereinafter, a conventional power-up circuit having the above problem will be described in detail with reference to the accompanying drawings.

1 illustrates a conventional power-up circuit diagram, wherein a plurality of P-channel MOS transistors, each gate of which is commonly connected to a ground potential Vss and connected in series between an external voltage applying terminal and a first node N1, An N-channel MOS transistor MN1 having a gate connected to the first node N1, a ground potential, and a source connected thereto, and a potential of the first node N1 is commonly applied to a gate, and is connected between an external voltage applying terminal and a ground potential. A P-channel MOS transistor MP1 connected in series by a second node N2 and an N-channel MOS transistor MN2 to ensure a portion of the power-up signal to be 'low' which is enabled Up detection unit 10,

A buffering unit comprising an even number of CMOS inverters connected in series between the second node N2 and an output node for outputting a power-up signal pwrup for delaying and outputting a signal of the second node N2 for a predetermined time ( 20).

In the conventional power-up circuit having the above configuration, when a predetermined voltage is applied to an external voltage applying terminal in a normal state, a plurality of P-channel MOS transistors having a gate applied to the ground potential in common are all turned on, and thus the first node ( N1) is 'high' and the P-channel MOS transistor MP1 of the power-up sensing unit 10, in which the 'high' potential of the first node N1 is applied to the gate in common, is turned off. The N-channel MOS transistor MN2 is turned on so that the 'high' potential of the first node N1 flows to the ground through the turned-on N-channel MOS transistor MN2 to 'low' at the second node N2. 'The potential is applied, and the' low 'potential of the second node N2 is delayed for a predetermined time after the even number of CMOS inverters forming the buffering unit 20, and then the power-up signal, which is an output signal of the power-up circuit, Output as low.

However, in a worst case condition (such as when the temperature suddenly rises or the power is noisy), even one of the plurality of series-connected P-channel MOS transistors of the power-up detector 10 may be turned off. The first node N1 receives a 'low' potential to turn on the P-channel MOS transistor MP1 of the power-up detector 10, and turn off the N-channel MOS transistor MN2. As a result, the second node N2 becomes 'high', and thus the power-up signal pwrup output through the buffering unit 20 outputs 'high'.

As a result, a power-up signal (pwrwp) having a 'high' output may fail to set the initial value of the input buffer normally under the worst condition, and the initial value of the input buffer may be set incorrectly. There was a problem that the unnecessary current consumption is increased by enabling the signal that should not be.

That is, in the conventional power-up circuit, when the power is turned on, the power-up detector 10 detects the power-up circuit and enables the power-up circuit. At this time, the power-up signal pwrup is applied to each input buffer when the power is turned on. Going to determine the initial value of the latch, in order to determine the initial value of each latch, there should be a section in which the power-up signal (pwrup) 'low' from the power is turned on. If there is no such 'low' period, the initial value of each input buffer is set incorrectly, and a signal that should not float in the standby mode is displayed, which causes unnecessary current consumption.

FIG. 2 is a graph showing a result of simulating a conventional power-up circuit to an initial value in a worst case condition, in which the power-up signal pwrup becomes 'low' when applying an external voltage VEXT. Indicates that there is no section. As a result, the initial value of the input buffer cannot be set correctly.

3 illustrates a graph of a simulation result of a conventional power-up circuit against noise under worst case conditions, and the conventional power-up circuit is affected only by an output signal of the power-up detector 10. Since the power-up signal is determined, it indicates that the power is turned off at about 1.4V when the power-up detector 10 is severely shaken by the noise.

3 shows that the conventional power-up circuit is not influenced by the power-up detection unit 10 and there is no device for maintaining the power-up signal pwrup. The problem is that power is killed in the middle.

Accordingly, the present invention has been made to solve the above problem, and an object of the present invention is to feed back the power-up signal so that the initial value can be reliably ensured when the power-up signal is set so that the power-up signal is 'low'. The present invention provides a power-up circuit that can guarantee a period in which the power-up signal is 'low' by not allowing the power-up signal to rise even when the power-up detector is enabled.

1 is a conventional power-up circuit diagram.

FIG. 2 is a graph showing the initial value of the power-up circuit of FIG. 1 under worst case conditions.

FIG. 3 is a graph of the noise of the power-up circuit of FIG. 1 under worst case conditions.

4 is a power-up circuit diagram according to an embodiment of the present invention.

5 is a simulation result of the power-up circuit of FIG.

FIG. 6 is a graph of a simulation of the power-up circuit of FIG. 4 against noise under worst case conditions. FIG.

* Explanation of symbols for main parts of the drawings

10: power-up detector 20: buffering unit

30: power-up enable part 40: latch part

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

4 is a diagram illustrating a power-up circuit according to an embodiment of the present invention. The power-up signal is detected by a power-on signal and enables the power-up signal pwrup. Power-up detection unit 10 for setting,

The following circuit is operated only when the power-up signal is 'low' by receiving the output signal and the feedbacked power-up signal (pwrup) of the power-up detector 10 so that the power-up signal is “low”. In order to ensure the 'in period, the P-channel MOS transistor MP1 connected in series between an external voltage VEXT applied terminal and the first node N1 and a power-up signal is applied to a gate, and the power-to-gate. A power-up enable unit 30 including a P-channel MOS transistor MP2 to which an output signal of the up-sensing unit 10 is applied,

CMOS comprising a P-channel MOS transistor MP3 and an N-channel MOS transistor MN1 connected to the first node N1 in common with the respective gates and connected by an second node N2 between an external voltage applying terminal and a ground potential. A type inverter and the second node N2 are commonly connected to respective gates, and are connected in series between an external potential applying terminal and a ground potential, and a connection node thereof is inputted to the node N1 so that the second node N2 is connected to the gate N2. A latch portion 40 composed of a CMOS inverter consisting of a P-channel MOS transistor MP4 and an N-channel MOS transistor MN2 for latching a potential;

Capacitor C1 connected between the power-up enable unit 30 and the ground potential to increase the stability by ensuring a power-up signal (pwrup) in the initial state,

Buffering for outputting a power-up signal, which is an inverted signal, made of an odd-numbered CMOS inverter between the second node N2 and the output terminal of the latch unit 40 by delaying the potential of the second node N2 for a predetermined time. It consists of a part 20.

In the power-up circuit according to the embodiment of the present invention having the above configuration, the power-up enable unit outputs a power-up signal pwrup 'low' in a normal state so that the power-up signal is fed back. The P-channel MOS transistor MP1 of 30 is turned on and the P-channel MOS transistor MP2 is also turned on by the 'low' output of the power-up detector 10 so that the first node is temporarily 'high'. Although the potential is applied, the first node N1 is directly transitioned to 'low' by the grounded capacitor C1 so that the P-channel MOS transistor MP3 having the first node N1 connected to the gate is As long as the turn-on and N-channel MOS transistor MN1 is turned off and the power-up signal pwrup has a low state at the second node N2 of the latch portion, the 'high' potential is maintained. The 'high' potential of the second node N2 is half through the buffering unit 20 implemented with an odd CMOS inverter. It is delayed after a certain period of time a power-up, and outputs the signal to the enable state of the 'low'.

However, in the worst case condition (such as when the temperature suddenly rises or the power is noisy), the power-up detection unit 10 cannot set the 'low' portion of the power-up signal pwrup. In the same situation, when the signal of the power-up sensing unit 10 is transmitted, a power-up signal pwrup of 'high' potential is applied to the gate of the P-channel MOS transistor MP1 of the power-up enable unit 30. Since the P-channel MOS transistor MP1 is turned off, the circuit below does not operate, so that the power-up signal pwrup of the output terminal is outputted as 'low'.

FIG. 5 is a graph showing a result of simulation of the power-up circuit of the present invention shown in FIG. 4 with respect to an initial value under a worst case condition. Indicates that there is a section where the power-up signal pwrup initially goes 'low'.

6 is a graph showing a result of simulation of the power-up circuit according to the present invention with respect to noise under the worst condition, and shows that the power is maintained without dropping even when the power is severely shaken by the noise.

With the above configuration and operation, the power-up circuit of the present invention feeds back a power-up signal (pwrup) having a 'high' output under worst case conditions so that the power-up signal is not in a 'low' state. Even if the sensing unit 10 is enabled, the power-up signal is transferred to 'low' by turning off the P-channel MOS transistor MP1 of the power-up enable unit 30.

In addition, by implementing the latch unit 40 additionally, the power is shaken due to the noise so that the power-up signal operates normally even when the power-up branch unit 10 malfunctions. By adding the capacitance (C1) to ensure the power-up signal (pwrup) in the initial state 'low' is characterized by improved stability.

As described above, the power-up circuit according to the present invention outputs the power-up signal 'low' even under the worst conditions so that the initial value of the input buffer can be set accurately, thereby reducing unnecessary current consumption. It has a very good effect that can be prevented.

In addition, by implementing the latch unit and the capacitor additionally, the power is shaken due to the noise so that the power-up signal can operate normally even if the power-up detection unit malfunctions, and the power-up signal is enabled in the initial state. Guaranteed to increase the stability.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (2)

In a semiconductor memory device, An output terminal for outputting a power-up signal for operating a plurality of input buffers, Power-up sensing means for sensing power and enabling a power-up signal; The operation is controlled by the power-up signal and the power-up detection signal, respectively, and includes first and second switch elements implemented with P-channel MOS transistors to operate only when the power-up signal is 'low'. Power-up enable means for supplying the power-power voltage to a first node by operation of first and second switch elements; Latch means connected between the first node and a second node to latch a signal of the second node; And an output driving means between the second node and the output terminal. The method of claim 1, And the latching means and the buffering means are implemented with a CMOS inverter.

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