KR100780639B1 - Power up circuit of semiconductor device - Google Patents

Abstract

A power up circuit of a semiconductor device is provided to perform a test by changing a target voltage level without a focused ion beam or revision of a mask of a circuit. A control signal generation unit(100) generates a control signal in a test mode. A level sensing unit(200) changes a target voltage level in response to the control signal, and senses whether an external power supply voltage exceeds the target voltage level or not. A driver(300) drives an output signal of the level sensing unit and then outputs the output signal as a power- up signal.

Description

Power up circuit of semiconductor device {POWER UP CIRCUIT OF SEMICONDUCTOR DEVICE}

1 is a power up circuit for testing a power up signal by varying a target voltage level in the related art.

2 is a block diagram of a power up circuit for varying a target voltage level in a test mode in accordance with the present invention.

FIG. 3 is a circuit diagram illustrating a first embodiment of the level detecting unit of FIG. 2. FIG.

4A and 4B are circuit diagrams for explaining a second embodiment according to the present invention.

* Explanation of symbols for the main parts of the drawings

100: control signal generator

200: level detection unit

300: driver

400: fuse circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a power up circuit of a semiconductor device for controlling a target voltage level of a power up signal.

In general, the semiconductor device does not operate in response to the voltage level of the external power supply voltage VDD as soon as the external power supply voltage VDD is input, but the external power supply voltage VDD is above a predetermined target voltage level. It is operated after rising to. If the internal circuit operates after reaching the target voltage level after the external power supply voltage VDD is applied, the entire semiconductor device may be destroyed due to latch-up. For this reason, semiconductor devices typically have to be equipped with a power-up circuit.

Such a power-up circuit outputs a power-up signal (hereinafter referred to as "PWRUP") of logic "low" until a predetermined voltage level after the external power supply voltage VDD is applied, and the external power supply voltage VDD is a target. When the voltage level is stabilized or higher, a power-up signal PWRUP that transitions to logic 'high' is output. The internal circuit operates stably in response to the power up signal PWRUP.

Therefore, the target voltage level is an important factor in determining the operation point of the semiconductor device. In recent years, the target voltage level has been tested to change the target voltage level to find a more efficient and stable power-up signal PWRUP transition point.

1 is a power-up circuit for testing a power-up signal PWRUP by varying a target voltage level.

In FIG. 1, an output signal of the level detecting unit 20 and the level detecting unit 20 for detecting that the external power supply voltage VDD rises above the target voltage level is driven and output as a power-up signal PWRUP. The driver 30 is shown.

The level sensing unit 20 includes a plurality of resistors R1, R2, R3, R4, R5, and R6 and metal options MT1 and R1 connected in parallel to the resistors R1, R2, R5, and R6, respectively. MT2, MT3, MT4, and NMOS transistor NM1 that is turned on when the external power supply voltage VDD rises above the target voltage level.

The driver 30 has a source-drain formed between an external power supply voltage terminal VDD and an output terminal of the power-up signal PWRUP, and a PMOS transistor PM1 gated to the ground voltage terminal VSS, and a power-up signal ( A source-drain is formed between the output terminal of the PWRUP and the ground voltage terminal VSS, and the NMOS transistor NM2 receives the output signal of the level sensing unit 20 as a gate.

Looking at the operation, the external power supply voltage (VDD) is gradually increased at '0V'. At this time, the NMOS transistor NM2 of the driver 30 is turned on so that the power-up signal PWRUP becomes logic 'low'. Thereafter, when the external power supply voltage VDD reaches the target voltage level, the NMOS transistor NM1 of the level sensing unit 20 is turned on to turn off the NMOS transistor NM2 of the driver 30. The up signal PWRUP transitions to logic 'high'.

That is, the target voltage level is determined by the resistance value of the level sensing unit 20. Therefore, conventionally, when a test for varying the target voltage level is performed, desired portions of the metal options MT1, MT2, MT3, MT4 are cut off or the circuit masks are revised. In other words, the resistance value is varied by selectively bypassing the resistors R1, R2, R5, and R6, and eventually, the target voltage level is varied.

As described above, the target voltage level of the power-up signal PWRUP is varied by conventionally changing a mask of a circuit or cutting a desired place among the metal options MT1, MT2, MT3, MT4. However, reworking the mask of the circuit has the problem of enormous time and cost. In addition, since the connected ion beam (FIB), which is one of the devices that cuts off the metal option, is an expensive device, there is also a problem in that it costs much.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and provides a power-up circuit of a semiconductor device capable of varying and testing a target voltage level without a connection ion beam (FIB) or revision. There is this.

According to an aspect of the present invention for achieving the above object, the control signal generating means for generating a control signal in the test mode; Level sensing means for varying a target voltage level in response to the control signal and detecting that an external power supply voltage is equal to or greater than the target voltage level; And a driver for driving the output signal of the level sensing means and outputting the output signal as a power-up signal. Preferably, the control signal generating means is characterized in that it comprises a counter for generating a plurality of control signals that are sequentially activated.

Control signal generating means for generating first and second control signal groups in a test mode, according to another aspect of the present invention for achieving the above object; First voltage distribution means for raising a target voltage level in response to the first control signal group; Second voltage distribution means for lowering the target voltage level in response to the second control signal group; Selection transfer means for selectively transferring output signals of the first and second voltage distribution means; Sensing means for detecting that an external power supply voltage is equal to or greater than a target voltage level defined by the first or second voltage distribution means according to the output signal of the selection transfer means; And a driver for driving the output signal of the sensing means and outputting the output signal as a power-up signal.

Control signal generation means for generating a control signal in a test mode, according to another aspect of the present invention for achieving the above object; Level sensing means for varying a target voltage level in response to the control signal and detecting that an external power supply voltage is equal to or greater than the target voltage level; A driver for driving the output signal of the level sensing means and outputting it as a power-up signal; And a fuse circuit programmed according to the test result to set the target voltage level.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2 is a block diagram of a power-up circuit for varying a target voltage level in a test mode according to the present invention.

2, a control signal generation generating a control signal CTRL <0>, CTRL <1>, ..., CTRL <N>, where N is a natural number, by receiving a test signal TM_EN that is activated in a test mode. The level detecting unit 100 detects that the external power supply voltage VDD is equal to or greater than the target voltage level that is changed by the control signals CTRL <0>, CTRL <1>, ..., CTRL <N>. And a driver 300 for driving the output signal of the level sensing unit 200 and outputting the output signal as a power-up signal PWRUP, and for setting a target voltage level programmed and selected according to the test result in the test mode. Fuse circuit 400 is shown.

Here, the control signal generator 100 and the fuse circuit 400 are enabled by the test signal TM_EN. For example, when the test signal TM_EN is logic 'high' in the test mode, the control signal generator 100 is activated to control the plurality of control signals CTRL <0>, CTRL <1>, ..., CTRL <N. >, And the target voltage level is varied according to the control signals CTRL <0>, CTRL <1>, ..., CTRL <N>. The control signal generator 100 may be a counter that is sequentially activated according to the configuration of the level detector 200. When the test signal TM_EN is logic 'low' in the normal mode other than the test mode, the fuse circuit 400 is activated to control the signals CTRL <0>, CTRL <1>, ... , CTRL <N>) will be output. The control signal generation unit 100 and the fuse circuit 400 will be described in more detail with reference to FIGS. 3, 4A, and 4B.

3 is a circuit diagram illustrating a first embodiment of the level sensing unit 200 of FIG. 2.

Referring to FIG. 3, the level sensing unit 200 according to the first embodiment is formed between the external power supply voltage terminal VDD and the output node D1 to provide a plurality of resistors for distributing the external power supply voltage VDD. A voltage divider 210 including R <0>, R <1>, ..., R <N>, R <N + 1>, R <N + 2>, and a plurality of resistors R < First switching unit including a plurality of NMOS transistors NM <0>, NM <1>, ... NM <N> corresponding to 0>, R <1>, ..., R <N> And a second switching unit 230 formed between the output node D1 and the ground voltage terminal VSS and turned on when the external power supply voltage VDD rises above the target voltage level. Here, the second switching unit 230 is source-drain connected between the output node D1 and the ground voltage terminal VSS, and has a common node of a resistor of 'R <N + 1>' and 'R <N + 2>'. An NMOS transistor N1 gated to it.

In addition, the driver 300 has a source-drain formed between an external power supply voltage terminal VDD and an output terminal of the power-up signal PWRUP, and a PMOS transistor P1 gated to the ground voltage terminal VSS, and a power-up signal ( A source-drain is formed between the output terminal of the PWRUP and the ground voltage terminal VSS, and the NMOS transistor N2 receives the output signal of the level sensing unit 20 and is the same as the conventional configuration of FIG.

The first embodiment according to the present invention conventionally constitutes a plurality of NMOS transistors (NM <0>, NM <1>, ... NM <N>) instead of metal options. One end of each NMOS transistor NM <0>, NM <1>, ... NM <N> is connected to an external power supply voltage terminal VDD. The other end of the 'NM <0>' NMOS transistor is connected to the common node of the 'R <0>' resistor and the 'R <1>' resistor, and the other end of the 'NM <1>' NMOS transistor is 'R'. The other end of the 'NM <2>' NMOS transistor is connected to the common node of the 'R <2>' and 'R <3>' resistors. The other end of the 'NM <N>' NMOS transistor is connected to the common node of the 'R <N>' resistor and the 'R <N + 1>' resistor. The gate of each NMOS transistor is connected to each control signal CTRL <0>, CTRL <1>, ..., CTRL <N>.

Therefore, in response to the control signals CTRL <0>, CTRL <1>, ..., CTRL <N>, the plurality of resistors R <0>, R <1>, ..., R <N> are Bypass selectively, the target voltage level is varied. The same configuration as the first embodiment requires 'N' control signals, and in this case, the control signal generation unit 100 of FIG. 2 includes a 'N' bit counter for sequentially activating the 'N' bits. Can be. In other words, in setting the target voltage level, only the first 'CTRL <0>' control signal is logic 'high', and only the 'NM <0>' NMOS transistor is turned on to perform the test, and then the 'CTRL <1>' Only the control signal is logic high, and only the NM <1> NMOS transistors are turned on to perform the test. In this way, if the 'CTRL <N>' control signal becomes logic 'high' and only the 'NM <N>' NMOS transistor is turned on to perform the test, the test mode is terminated.

That is, according to the control signals CTRL <0>, CTRL <1>, ..., CTRL <N> sequentially activated, the resistance value of the voltage divider 210 decreases, and as a result, the target voltage level is gradually lowered. Test will be performed. If the control signals CTRL <0>, CTRL <1>, ..., CTRL <N> are sequentially activated from the 'CTRL <N>' control signal to the 'CTRL <0>' control signal, the target voltage You can test as you level up. Such a test may obtain more regular test results based on the counted control signal.

The fuse circuit 100 of FIG. 2 is programmed and fuse-cut according to the test result, and in the normal mode, the control signals CTRL <0> and CTRL <1 that generated target voltage levels obtained through the above test. >, ..., CTRL <N>). That is, the fuse circuit 100 is programmed according to the test result to set a desired target voltage level.

4A and 4B are circuit diagrams for describing a second embodiment according to the present invention.

The level sensing unit 400 and the driver 300 of FIG. 4A are illustrated. The level detecting unit 400 of FIG. 4A includes a first voltage divider for raising a target voltage level in response to the first control signal groups CTRL <0>, CTRL <1>, CTRL <2>, and CTRL <3>. 410, a second voltage divider 420 for lowering a target voltage level in response to the second control signal group CTRL <4>, CTRL <5>, CTRL <6>, and CTRL <7>; An external power supply voltage according to an output signal of the selection transmitter 430 and the selection transmitter 430 for selectively transferring any one of the target voltage levels generated by the first and second voltage dividers 410 and 420. The detector 440 detects that the VDD is equal to or higher than the target voltage level.

Here, the first voltage divider 410 is formed between the external power supply voltage terminal VDD and the first output node D1, and at least one resistor R1, R2, R3, R4, R5 and each resistor R1. , The first variable resistor unit 411 including the first switching units NM1, NM2, NM3, and NM4 corresponding to R2, R3, and R4, and the first output node D1 and the second output node D2. The first fixed resistance portion 412 is formed between the (). Here, one end of each of the NMOS transistors NM1, NM2, NM3, and NM4 of the first variable resistor unit 411 is connected to an external power supply voltage terminal VDD. The other end of the 'NM1' NMOS transistor is connected to the common node of the 'R1' and 'R2' resistors, and the other end of the 'NM2' NMOS transistor is connected to the common node of the 'R2' and 'R3' resistors. The other end of the 'NM3' NMOS transistor is connected to the common node of the 'R3' resistor and the 'R4' resistor, and the other end of the 'NM4' NMOS transistor is connected to the common node of the 'R4' resistor and the 'R5' resistor. Connected. The first control signal group CTRL0, CTRL1, CTRL2, and CTRL3 are gated to the corresponding NMOS transistors NM4, NM3, NM2, and NM1. Therefore, the target voltage level is variable by selectively bypassing the resistors R1, R2, R3, and R4 in accordance with the first control signal groups CTRL0, CTRL1, CTRL2, and CTRL3.

The second voltage divider 420 includes a second fixed resistor 421 formed between the external power supply voltage terminal VDD and the third output node D3, and a third output node D3 and the fourth output node. A second switching unit NM9, NM10, NM11, formed between the output node D4 and corresponding to at least one resistor R8, R9, R10, R11, R12 and each of the resistors R9, R10, R11, R12, A second variable resistor part 422 including NM12 is provided. Here, one end of each of the NMOS transistors NM1, NM2, NM3, and NM4 of the second variable resistor unit 422 is connected to the fourth output node D4. The other end of the 'NM9' NMOS transistor is connected to the common node of the 'R8' and 'R9' resistors, and the other end of the 'NM10' NMOS transistor is connected to the common node of the 'R9' and 'R10' resistors. The other end of the 'NM11' NMOS transistor is connected to the common node of the 'R10' resistor and the 'R11' resistor, and the other end of the 'NM12' NMOS transistor is connected to the common node of the 'R11' resistor and the 'R12' resistor. do. The second control signal group CTRL4, CTRL5, CTRL6, and CTRL7 are gated to the corresponding NMOS transistors NM9, NM10, NM11, and NM12. Therefore, the target voltage level is variable by selectively bypassing the resistors R9, R10, R11, and R12 in accordance with the second control signal groups CTRL4, CTRL5, CTRL6, and CTRL7.

In addition, the selection transfer unit 430 may output a selection signal LEVEL_SEL for selecting the rising and falling of the target voltage level, and the first and third parts in response to the selection signal LEVEL_SEL. The first selector 432 for outputting any one of the voltage levels generated at the output nodes D1 and D3 and the second and fourth output nodes D2 and D4 in response to the selection signal LEVEL_SEL. A second selector 433 outputs any one of the voltage levels.

Here, the first and second selectors 432 and 433 may include a first transfer gate TG1 selectively transmitting the first output node D1 and a second selectively transmitting the second output node D2. A transfer gate TG2, a third transfer gate TG3 selectively transferring the third output node D3, and a fourth transfer gate TG4 selectively transferring the fourth output node D4. .

In addition, the selection signal output unit 431 may include a first NOR gate NOR1 receiving the control signals 'CTRL <4>' and 'CTRL <5>', and 'CTRL <6>' and 'CTRL <7>'. A second NOR gate NOR2 for receiving the control signal and an AND gate NAD1 for receiving the output signals of the first and second NOR gates NOR1 and NOR2 to increase the target voltage level. The select signal LEVEL_SEL is output low and the select signal LEVEL_SEL is logic high when the target voltage level is lowered.

In addition, the sensing unit 440 is sus-drain connected between the output terminal of the second selector 433 and the ground voltage terminal VSS, and the output terminal of the first selector 432 is gated to the NMOS transistor NM13. ).

4B shows an 8-bit counter, which is a control signal generator 500 in accordance with a second embodiment of the present invention.

The 8-bit counter of FIG. 4B has a plurality of control signals CTRL <0>, CTRL <1>, CTRL <2>, and CTRL <3> sequentially activated in response to the test signal TM_EN activated in the test mode. , CTRL <4>, CTRL <5>, CTRL <6>, CTRL <7>. That is, when the test signal TM_EN is activated, 'CTRL <0>' only the control signal is logic 'high' and performs one test, and then 'CTRL <1>' only the control signal is logic 'high'. One test is performed, and 'CTRL <2>' only the control signal is logic 'high' and another test is performed. Thus, the plurality of control signals CTRL <0>, CTRL <1>, CTRL <2>, CTRL <3>, CTRL <4>, CTRL <5>, CTRL <6>, and CTRL <7> are sequentially The logic 'high' changes the resistance values of the first and second variable resistor parts 411 and 422.

In other words, the 'CTRL <0>' control signal is logic 'high', and then the 'CTRL <1>', 'CTRL <2>', and 'CTRL <3>' control signal is logically 'high'. When the first variable resistor portion 411 is gradually increased resistance value. On the other hand, the selection signal LEVEL_SEL becomes logic 'low' so that the first and second transfer gates TG1 and TG2 are activated and sensed according to the voltage levels generated by the first and second output nodes D1 and D2. The NMOS transistor NM13 of the unit 440 is turned on / off.

Then, the 'CTRL <4>' control signal is logic 'high', and then 'CTRL <5>', 'CTRL <6>', and 'CTRL <7>' control signal are logically 'high'. When the second variable resistor unit 422 is gradually increased in resistance. Here, as the resistance value of the second variable resistor unit 422 increases, the target voltage level decreases as the target voltage level increases as the resistance value of the first variable resistor unit 411 increases. On the other hand, the selection signal LEVEL_SEL becomes logic 'high' so that the third and fourth transfer gates TG3 and TG4 are activated and sensed according to the voltage levels generated by the third and fourth output nodes D3 and D4. The NMOS transistor NM13 of the unit 440 is turned on / off.

Here, the case of raising the target voltage level and the case of lowering the target voltage level are relative meanings. For example, when the 'CTRL <0>' control signal is logic 'high' and when the 'CTRL <4>' control signal is logic 'high', if the target voltage level is the same as '1.2V', the logic is sequentially The target voltage level is gradually increased by the 'CTRL <0>' control signal, the CTRL <1> control signal, the 'CTRL <2>' control signal, and the 'CTRL <3>' control signal, which are high. In addition, the target voltage level is controlled by the 'CTRL <4>' control signal, the CTRL <5> control signal, the 'CTRL <6>' control signal, and the 'CTRL <7>' control signal, which are sequentially logic 'high'. It will descend gradually.

After the test is performed by raising and lowering the target voltage level, the test result is obtained by using a fuse circuit (not shown) using simple fuse cutting as in the first embodiment. Signals such as the control signals CTRL <0>, CTRL <1>, CTRL <2>, CTRL <3>, CTRL <4>, CTRL <5>, CTRL <6>, and CTRL <7> It will be generated and normal operation in normal mode. That is, the fuse circuit (not shown) programmed according to the test result sets the desired target voltage level.

Such a circuit configuration according to the present invention can be used for all semiconductor devices requiring a test mode for varying a target voltage level, and may also be used for mobile.

As described above, in order to change the target voltage level of the power-up signal PWRUP, the target voltage level may be changed by using a device such as a connected ion beam (FIB), or by changing a mask of the circuit or by using a device such as a connected ion beam (FIB). Was variable. However, the present invention includes a MOS transistor in place of a conventional metal option, a control signal generator 100 for controlling the MOS transistor, and a signal for generating a target voltage level selected according to the test result, thereby generating the MOS transistor. Added a simple fuse circuit 400 to control the. In other words, it is possible to test a variable target voltage level without a connection ion beam (FIB) or revision, and generate a target voltage level desired by a simple fuse cutting according to the test result. An up signal PWRUP may be generated.

In addition, by configuring the control signal generation unit 100 as a counter (counter), it is possible to perform a regular test faster based on the counted control signal during the test.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above can save a lot of cost and time by eliminating the need to revise a mask of a circuit or using expensive connected ion beam (FIB) equipment when performing a test of varying a target voltage level. It can be effective. In addition, it is possible to obtain a regular test result faster based on the counted control signal.

Claims (21)

Control signal generating means for generating a control signal in a test mode; Level sensing means for varying a target voltage level in response to the control signal and detecting that an external power supply voltage is equal to or greater than the target voltage level; And A driver for driving the output signal of the level sensing means and outputting it as a power-up signal A power up circuit of a semiconductor device having a. According to claim 1, The control signal generating means further comprises a counter for generating a plurality of control signals which are sequentially activated. The method according to claim 1 or 2, The level detecting means, Voltage distribution means formed between an external power supply voltage terminal and an output node and distributing the external power supply voltage; First switching means connected in parallel to the voltage distribution means and responsive to the control signal; And A second switching means formed between the output node and the ground voltage terminal and turned on when the external power supply voltage rises above the target voltage level; A power up circuit of a semiconductor device having a. The method of claim 3, wherein The voltage dividing means includes at least one resistor connected in series. The method of claim 4, wherein And the first switching means includes a MOS transistor connected in parallel to the at least one resistor and receiving the control signal as a gate. The method of claim 4, wherein And the second switching means includes an NMOS transistor source-drain connected between the output node and the ground voltage terminal and gated to any one node connected to the at least one resistor. Control signal generating means for generating first and second control signal groups in a test mode; First voltage distribution means for raising a target voltage level in response to the first control signal group; Second voltage distribution means for lowering the target voltage level in response to the second control signal group; Selection transfer means for selectively transferring output signals of the first and second voltage distribution means; Sensing means for detecting that an external power supply voltage is equal to or greater than a target voltage level defined by the first or second voltage distribution means according to the output signal of the selection transfer means; And Driver for driving the output signal of the sensing means to output as a power-up signal A power up circuit of a semiconductor device having a. The method of claim 7, wherein And the control signal generating means further comprises a counter for generating the first and second control signal groups which are sequentially activated. The method according to claim 7 or 8, The first voltage distribution means, A first variable resistor unit formed between the external power supply voltage terminal and the first output terminal and including at least one resistor and a first switching unit connected in parallel to the resistor; And A first fixed resistor unit formed between the first output terminal and the second output terminal; A power up circuit of a semiconductor device comprising the. The method of claim 9, And the first switching unit includes a MOS transistor configured to gate input the first control signal group, respectively. The method of claim 9, The second voltage distribution means, A second fixed resistor unit formed between the external power supply voltage terminal and a third output terminal; And A second variable resistor unit formed between the third output terminal and the fourth output terminal and including at least one resistor and a second switching unit connected in parallel to the resistor; A power up circuit of a semiconductor device comprising the. The method of claim 11, wherein And the second switching unit includes a MOS transistor configured to gate input the second control signal group, respectively. The method of claim 11, wherein The selection delivery means, Means for receiving the second control signal group and outputting a selection signal; A first selector configured to output one of voltage levels generated at the first and third output terminals in response to the selection signal; And A second selector configured to output one of voltage levels generated at the second and fourth output terminals in response to the selection signal; A power up circuit of a semiconductor device comprising the. The method of claim 13, And the selection signal has a first logic level when raising the target voltage level and a second logic level when lowering the target voltage level. The method of claim 14, The first selector transfers the generated voltage level to the first output terminal when the selection signal is the first logic level, and transfers the generated voltage level to the third output terminal when the selection signal is the second logic level. A power up circuit of a semiconductor device. The method of claim 14, The second selector transfers the generated voltage level to the second output terminal when the selection signal is the first logic level, and transmits the generated voltage level to the fourth output terminal when the selection signal is the second logic level. A power up circuit of a semiconductor device. The method of claim 13, And the sensing means includes an NMOS transistor having a source-drain connected between an output terminal of the second selector and a ground voltage terminal, and an output terminal of the first selector connected to a gate. Control signal generating means for generating a control signal in a test mode; Level sensing means for varying a target voltage level in response to the control signal and detecting that an external power supply voltage is equal to or greater than the target voltage level; A driver for driving the output signal of the level sensing means and outputting it as a power-up signal; And A fuse circuit programmed according to the test result to set the target voltage level A semiconductor device comprising a. The method of claim 18, The control signal generating means further comprises a counter for generating a plurality of control signals that are sequentially activated. The method of claim 18 or 19, And the level detecting means raises and lowers the target voltage level in response to the control signal. The method of claim 20, The fuse circuit is a semiconductor device, characterized in that the fuse cutting (fusecutting) method.

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